Electronic – DG flip-flop behavior

This looks like a homework question, which I won't answer. But here are some pointers:

• You cannot represent more states than what you have available -> that means that you will have to go to the next higher state (i.e. 2 FF's for 4 states) or use only one FF per state. (i.e. FF #1 correlates directly to A).

• option #1 ( 2 FF's and 4 states) is more economical but you have to make sure that the unused state does n't not get activated and then locks out.

  • you might draw this as a 4th state "D" with loops back to itself.
  • what is generally considered safe design is that you always have explicit transitions AWAY from the unused state in case it gets activated.

• option #2 uses more FF's but cannot have any hidden states.

  • it is inherently safer.
  • it is known as a "one hot" design and thermometer codes are examples of this.

Your choice of states "A = 00" etc. will make the design simpler or more complicated. SO may want to go with what you decribe or you may want to go with state C = "10". You should look at all possibilities.

The first SM, only uses 0 or 1 as an input because it only has one input variable. They should have used a variable for clarity anyways. You'll notice in the table that it is marked as "x" but not in the diagram.

The hold time is the time the input must be stable after the clock edge for the data to be sampled correctly by the clock edge. In many cases it is zero, but let's say it is 2 nsec. If your contamination time is 1nsec, it means that after 1nsec the output of the previous FF (input of the next one) started to chage => hold time of the second FF was violated