Electronic – Dielectric Loss for Constant Impedance

Two 50ohm Stripline traces in FR4 where one is very skinny with close GND planes, and another where traces are very wide with far GND plane separation.

Most likely, the skinnier trace will have higher insertion loss, but it's due to higher trace resistance, not dielectric loss.

Dielectric loss does not usually dominate the trace loss, unless you try to operate at too high a frequency with a poorly chosen material. In which case, the solution is use a better material, not try to adjust the geometry to make up for it.

Edit

OK, I've never seen this analyzed because, like I said above, it's usually not the dominant source of loss in a system.

One way to look at this is, the conductance per unit length of the microstrip is very nearly going to depend only on the ratio of trace width \$W\$ to height above the ground plane \$H\$.

Unfortunately, there are no closed-form formulas to determine the \$Z_0\$ of microstrip from the geometry. One common approxmation formula (source) is

$$Z_0 \approx \frac{120\pi}{\sqrt{\epsilon_{eff}}\left[\frac{W}{H}+1.393+\frac{2}{3}\ln\left(\frac{W}{H}+1.444\right)\right]}\ {\rm\Omega}$$

with

$$\epsilon_{eff}= \frac{\epsilon_r+1}{2}+\frac{\epsilon_r-1}{2}\left(1+12\frac{H}{W}\right)^{-1/2}$$

This approximation is valid when \$\frac{W}{H}\ge 1\$.

Since this formula depends only on the ratio \$\frac{W}{H}\$, to the extent it's accurate, we shouldn't expect the trace conductance to depend on the geometry chosen for a given substrate.

Even if (as we know) the approximation isn't perfectly accurate, we can infer that any change in conductance as we adjust the geometry will be fairly small.

I should add, that the particular approximation I chose neglects any effect from the thickness of the copper trace. You can find other approximation formulas that do consider this effect, and they can give you some idea how the geometry will vary from a constant \$\frac{W}{H}\$ as you scale.

As you move to very thin substrates, the trace thickness will have maximum impact on \$Z_0\$. The effect is to increase the trace capacitance, thus reducing the \$\frac{W}{H}\$ required to achieve a given \$Z_0\$. Reducing \$\frac{W}{H}\$ should reduce the trace conductance.

This implies that smaller geometries will have at least slightly reduced dielectric losses. However, smaller geometries will for sure increase resistive losses, and I've never heard any recommendation to try to improve overall system performance by using smaller geometries to reduce dielectric loss.