Hardware description language describes our circuit but what does Hardware Verification Language do? How does it verify the design?
Electronic – Difference between HVL and HDL
system-verilogverilog
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Best Answer
Hardware verification languages like vera, e and later SystemVerilog and SystemC were created to make the verification process more efficient. The story goes that as per Moore's law, the design size and thus its complexity is almost doubling every 18 months. In the early days of design when even microprocessors were actually drawn as schematics, no verification as exists now was performed before actually producing the silicon. Well of course, now we use computers to verify our design, but how did they verify the first computer? lol
In those days, when a full design is split into blocks, different people would use their own brain to design, verify and also simplify the design. If you would have told somebody that someday there would a tool in which you just type in some text and it will synthesize and simplify the circuit automatically, they would laugh at you. I read this in an actual book. However, things changed as designs became more complex and the design speed increased. Automating any task means removing human intervention and thus eliminating potential of human induced error. More complex means that human induced error is more likely. By this time, doing all design by hand was inefficient, people moved from hand drawing (yes actual physical drawing) to schematics on a computer to do the design. Later came the HDL which provided a much more efficient way to design digital circuits and exchange designs, overtime the synthesis tools became quite robust as well, thus the need to do schematic design was, well, no more. Now we can verify small blocks like full adder and multiplexer our self. However, what about a complex design? At this point people use HDLs for verification. In this case, we create a "testbench" that applies a predetermined stimulus to a model of our design and the generated output is compared with the expected output provided by the designer. This is possible since the digital circuits follow Boolean logic, their output can be predicted. It is possible to write a computer program which does this and this is exactly what happens in simulation.
Now to the question, why do we need HVLs? This is related to the software domain. As software became more and more complex, people moved from assembly to procedural languages like BASIC and C among others. However, writing and maintaining huge programs was still difficult. This is when people developed the object oriented programming paradigm. OOP is certainly a revolutionary development that has made it possible for computer programs to abstract a real world problem at unprecedented levels. It makes writing a program more efficient and also maintaining and expanding it.
Simulation is essentially a purely software based activity. When we use HDL to write a testbench we have to write precisely every single signal wiggle that must take place and at the time that it must take place. However, if we raise the level of abstraction to say writing a whole word (e.g a byte to data bus) at a time, writing testbench will become a lot quicker and less tedious. We can raise the level of abstraction even more, e.g with ethernet design we can write a whole packet at once and check a whole packet at once rather than single bits.
With HVLs they apply the OOP technique into the domain of hardware verification. They do so by making it possible to verify a design at a higher level of abstraction. At the same time, they contain features that are especially adapter for verification, rather than to write synthesize able code.
e.g SystemVerilog provides 2 important features. These are concurrent assertions and constrained-random testing. Like assertion checks that an expression is true at a give time, a concurrent assertion checks to make sure that a sequence in which signal toggles is correct. Rather than having to write every single piece of stimulus that must be applied to a design under verification, constrained-random testing applies all possible stimulus that fits constraint given by the verification engineer, overtime. This saves a lot of time in writing stimulus.