Please be aware that you are asking for trouble. A feedback resistance of 100MOhm will cause you all sorts of problems. You are talking such low currents that leakage will be a big problem, and if you are making a pc board, scrupulous cleanliness and removal of ALL traces of solder flux will be critical.
That said, do not use an integrator. Any problem a transimpedance amp has with leakage applies to integrators.
Furthermore, you have not described your system well enough to determine why your light levels are so low, and this opens up speculation about other potential problems. If your light levels are low because the source is far away, then you will have major problems with background and stray light. It's true you can deal with this (more optical effort, source modulation/demodulation, narrowband filters, etc), but you haven't given any indication of where to start.
I would suggest that you give serious thought to some form of optical enhancement, using a lens to focus incoming light on your detector and increase optical flux.
The practical integrator tries to compensate for two effects in non-ideal opamps:
Opamps have an input offset voltage \$V_{os}\$ that is due to transistor mismatch inside the opamp circuit. The easiest way of modelling the effect of this is to pretend that there is a DC voltage source in series with the + input of the opamp, equal to the voltage mismatch value.
With the ideal integrator, it will integrate this DC value up to the point that the opamp saturates, and the circuit is now useless until the capacitor is discharged.
With the practical integrator, \$R_f\$ turns the integrator into a low-pass filter with 3dB point (or cutoff frequency) of \$\frac{1}{2\pi R_f C}\$ (Hz). This means that frequencies far above this cutoff frequency (say 5x to 10x higher) will integrate perfectly, like expected. Frequencies below this cutoff, at steady state, will only see a gain (amplification) of \$R_f/R_i\$ (this is at steady state: to come back to our DC offset voltage, which is a DC value or 0 Hz frequency component, when you power on it'll start integrating normally, but slow down as it integrates and stop when it's been amplified by the gain).
Opamps have a bias current into or out of their two input pins. We call this value the input bias current, \$I_B\$, and it is DC. If you put a resistor at one input of the opamp, the bias current creates an input voltage that affects the opamp circuit's output. This is a DC error or DC offset at the output that is unwanted.
The resistor \$R_s\$ should be chosen so that the equivalent resistance looking out of the noninverting opamp input and inverting opamp input are equal. That way, the DC bias current into both inputs affect the + and - inputs equally, and they cancel out, leaving the output unaffected by the bias currents.
But the two currents into the input pins aren't equal (transistor mismatch rears its ugly head again). We call the difference between the two the input offset current, \$I_{os}\$. The difference is usually a lot smaller than the bias current, so doing this equivalent resistance matching at both opamp inputs still reduces the offset due to bias considerably.
Best Answer
First, note that the feedback and input pins are equivalent, they both have a resistive input into the summing node of the opamp. So whatever the opamp does, it does to the scaled sum of the input and the feedback signals, the scaling being set by the respective resistors.
Neither of these circuits is an integrator. An integrator would have a simple capacitor feedback without R2 or R6. However, for much of the frequency range, their response is mostly integrator-like, falling by 20dB per octave, with a 90 degree phase shift, when the capacitor is dominating the response.
So when is the capacitor not dominating the response? When the impedance is dominated by the resistor.
For the lefthand circuit, that's at high frequency. The gain will stop falling, and become flat above frequencies where C1 impedance falls below R2. As C1 cannot conduct DC, there needs to be some other path for DC feedback from output to input so that the output doesn't ramp off to a rail.
For the righthand circuit, it's at low frequency. The gain will stop rising and become flat below frequencies where C2 impedance rises above R6. Note this includes DC. This configuration is often used down to a very low frequency, with DC stability is ensured by R6.