Parallel Decoupling Capacitors – Different Types Explained


Page 29 of this DAC datasheet gives a typical operating circuit. I notice the power supplies have two decoupling capacitors in parallel: 100nF and 10μF.

What caught my eye is that there is a different symbol for each. (One has a curved edge, the other not.) As I understand, one is a "polarised" capacitor, and the other is not.

What is the qualitative difference between the two capacitors? Why are the types mixed in this application?

Best Answer

These are decoupling capacitors. They are there primarily for two reasons:

  1. Power supplies take time to respond to a demand for more current from the device. The capacitors act as a local reserve until the power supply responds.
  2. Digital logic devices demand current very abruptly (due to the steep logic edges). The inductance of the power supply traces makes it impossible to transfer a step in current from a power supply to the logic chip. To solve the problem, one places "decoupling" capacitors very close to the chip. As the remaining traces are very short, the edge problem is reduced.

The reason for the two different types of capacitors is as follows:

  1. The device apparently requires a 10µF decoupling capacitor. Capacitors of this size are typically electrolytic capacitors. The problem is: they respond quite slowly compared to the edge time.
  2. To solve the problem, one places a (typically) ceramic capacitor in parallel. To simplify the issue: they only exist in fairly small values.

Functioning: The ceramic capacitor (100nF) smoothes the edge time of any current requests from the device and the electrolytic capacitor (10µF) supplies the bulk of the current once it kicks in.