Electronic – digital input levels based on another circuit (using a transistor switch?)

First off, let's make some assumptions about the internal schematic that is unknown to you. There's a switch, given. And you've measured some voltages, with switch closed and open. These suggest to me something like this:

^{simulate this circuit – Schematic created using CircuitLab}

In other words, it sounds as though there is a pull-down resistor and that one side of the switch is tied to a nearly ideal \$+3.25\:\text{V}\$ voltage source. The reason I suggested \$33\:\text{k}\Omega\$ for the internal pull-down is because of your measurements. (Which may not be perfectly accurate, but probably sufficient.) You measured the voltage across the switch, when open, as \$3.15\:\text{V}\$. So, assuming that your voltmeter presents \$1\:\text{M}\Omega\$ impedance (a common assumption, lacking better information) this just means solving \$3.25\cdot\frac{x}{x+1\:\text{M}\Omega}=3.15\:\text{V}\$. And I get \$x\approx 31.7\:\text{k}\Omega\$. The pull-down might be \$10\:\text{k}\$, though. I don't know much about your meter. But the basic idea remains the same. It looks like there is a low-side pull-down resistor with the pushbutton attached at the high-side. The middle point is probably used internally (shown by the arrow) for whatever purposes -- which may be to simply power the internal circuit.

Now, before I move on, it's possible there isn't a pull-down resistor at all. It may be that this is the resistance presented by the circuit that the arrow points at, when the series resistance of your voltmeter is inserted between the power supply and the circuit. And if there is a pull-down resistor, then it in parallel with the circuit, presents something on the order of what I'm showing above. I just want to make sure that you don't assume I'm right. This is just a "model" that I'm using for illustration regarding your measurements.

The fact that a \$330\:\Omega\$ resistor can be added in series with SW just means that the circuit pointed at by the arrow probably doesn't draw more than \$1\:\text{mA}\$. You could play around with lots of different values. But I don't think it is necessary.

The main thing is this:

^{simulate this circuit}

The giant question-mark will now be filled in for you:

^{simulate this circuit}

That should use just about any junk box NPN pair. They do NOT need to be matched for \$\beta\$ or \$I_\text{SAT}\$ or much of anything else and it should work well over a wide ambient temperature range, as well.

The worst-case I/O pin leakage (configured as an input) for the ATmega32U4 is \$1\:\mu\text{A}\$. So the \$39\:\text{k}\Omega\$ resistors I've used shouldn't be affected by more than about \$40\:\text{mV}\$ due to I/O pin leakage. And I don't see a problem with that.

The circuit will work equally well on \$3.3\:\text{V}\$ and \$5.0\:\text{V}\$ power supply rails from the ATmega side. The I/O pin to the MCU from this circuit will simply use the given rail voltage, so the I/O voltage levels will match the requirements for the MCU I/O pin.

The circuit has substantial hysteresis, as well. Over temperature and mismatched BJTs, it should be at least a band that is \$200\:\text{mV}\$ wide -- but probably more than that by a fair margin.

There is an RC filter from the ATmega power supply (\$C_1\$ and \$R_7\$) to help avoid noise from the ATmega getting into the circuit. There's also an added capacitor (\$C_2\$) from the switch side to help moderate noise from that side, as well.

There's plenty of hysteresis in the circuit and so a lot of room for adjusting the resistor values (with the cost of somewhat less margin vs part variations.) So don't worry a lot about finding exact values.

The basic idea of the circuit isn't complex. If you only look at \$Q_1\$, \$Q_2\$, and \$R_3\$-\$R_6\$, you can see that the circuit looks "balanced."

But notice that if \$Q_1\$ is assumed to be on then \$Q_1\$'s collector pulls down on \$R_4\$ causing \$Q_2\$ to be off. With \$Q_2\$ off, it's collector is "open" and so \$R_3\$ and \$R_5\$ are free to supply base current to \$Q_1\$ so that it is, in fact, **on*. In other words, it's a stable assumption.

But also notice that the opposite is also true, if you assumed that \$Q_2\$ is on. Then that also would be a stable assumption for similar reasoning.

When you have a circuit like that, you don't know which way it will go.

Now, I added \$R_1\$ (which has another purpose I'll talk about later) and \$C_2\$ to one side. This means that upon power-up, \$Q_2\$ is pretty much guaranteed to be off and so the circuit will come up from power-on with \$Q_1\$ on and \$Q_2\$ off. Since the output is taken from \$Q_1\$'s collector, and since \$Q_1\$ powers up as on, the output to the I/O pin should be "LOW" and read as a "0". That's the case without anything else to disturb the circuit.

Then I added \$R_2\$ to bridge between this circuit and your other circuit's switch. When the other circuit powers up (its switch is turned on), then there will be about a \$2500\:\frac{\text{V}}{\text{s}}\$ rise in voltage on capacitor \$C_2\$ as current leaks in through \$R_2\$. So it doesn't take very long until \$Q_2\$'s base rises up enough to start turning it on. The current through \$R_2\$ will start out close to \$33\:\mu\text{A}\$ but as some current feeds the base of \$Q_2\$ and drains through \$R_1\$, it will droop down perhaps as low as \$25\:\mu\text{A}\$. Half that will be sunk through \$R_1\$, but enough remains to activate \$Q_2\$. And as \$Q_2\$ activates, it's collector will sink \$Q_1\$'s base supply via \$R_5\$. Since, at most, \$R_5\$ can only supply about \$120\:\mu\text{A}\$ and since even fully saturated and a \$\beta\approx 10\$ the base of \$Q_2\$ needs \$\le 12\:\mu\text{A}\$. And that is easily supplied. Not only that, as soon as \$Q_1\$ is pulled off by this process, \$R_6\$ and \$R_4\$ start supplying additional base current into \$Q_2\$ to snap it into the on state. And that's where it stays... so long as the external circuit continues to supply some added current.

Once the external device is turned off, \$R_2\$ no longer supplies any current. It might even withdraw some. But that depends on your external device. Let's assume no current via \$R_2\$. When that occurs, and here is the other purpose of \$R_1\$, \$R_1\$ will start to drain \$C_2\$ and will sink enough current to pull \$Q_2\$ off. So this is the other purpose of \$R_2\$. It's needed to allow the circuit to return to its default state.

Working its value out is important. Too small of a value and it will hold \$Q_2\$ off no matter what happens with the external circuit. Too large of a value and it can't sink enough current for the circuit to work properly and reset itself. So the value of \$R_2\$ is important -- it's value determines the centering position of the hysteresis -- and since there are transistor part variations and ambient temperature details to be worried about you don't want to mess with its value too much.

However, you can narrow the hysteresis by increasing the values of \$R_3\$ and \$R_4\$. A more narrow hysteresis will provide less noise rejection but it allows more room for change with \$R_2\$, too.

With the circuit above, run at temperatures below room temperature and up to \$55^\circ\text{C}\$ and over part variations of \$\beta\$ from 100 to 300 and a factor of 5 variation in saturation currents for the BJTs, the following hysteresis chart is simulated as:

(In the simulation, \$R_7\$ has the role of \$R_2\$ in the schematic shown above.)

This chart suggests that it's fairly safe to use junk box parts. And if you increased \$R_3\$ and \$R_4\$ to \$560\:\text{k}\Omega\$ the lower portion of the hysteresis band shifts from centered around \$6\:\mu\text{A}\$ to being centered around \$9\:\mu\text{A}\$. Plenty of hysteresis, still.