Electronic – Does an ALU always do add and sub, but only returns one of the results

8085alumultiplexer

Pretty simple question. Does an ALU internally always do multiple operations like add, sub, div, mul, … and you simply have to specify which result you want to return? I was told that it does that, but I wasn't able to find proof of that being correct. Though I found some graphics containing a multiplexer which from my understanding has basically one output and multiple inputs and by setting some special inputs you can pipe on input to the output. So that might be it, but I don't know enough about that to fully understand it.

I'm specifically wondering about the 8085 architecture's ALU in case it is special, but I'd also like to know about other ALUs if there are different ones.

Best Answer

Look up the age of the 8085. It dates from the era when every part of a circuit was hand optimised, and hand layout with tape and razor blade was still common (though likely Intel was using CAD systems). So it would have been designed to aggressively minimize the number of gates used. And as Tom says, you can add and subtract using the same circuit with a little care - so I think that gives you your answer.

From GBulmer's comment:

Can you see a way to produce multiple results (for example add and subtract) simultaneously, and select the correct answer with the fewer gates (or transistors) than logic producing only one result?

Personally, I can't. If you produce both answers, you need additional logic in the form of multiplexers to select the one you want.

Now I'm not going to run the experiment, but I suspect that if you write an ALU in VHDL, which follows this approach, a modern synthesis tool will spend a very long time (several seconds) and optimise it down to something close to the hand-optimised version.

To test this hypothesis, generate A+B, A-B, and a 2:1 multiplexer as separate modules, synthesise them separately and note resources. Then roll them up into a single design and re-run synthesis (you may need to enable optimisations, "optimise for area" and "flatten hierarchy"). The latter will be smaller : how close it is to a hand-minimised version I don't know : the challenge is set if anyone wants to add another answer!

Related Solutions

Electronic – How are various functions (eg. add, subtract, and, etc) implemented in ALU

While internally computing all the answers, and then using a mux to select among them will work, it certainly is not a minimal design.

Consider that you can bit-slice the problem; instead of a single block of logic with two 8 bit inputs, you could partition this as two 4-bit sections, as long as you can link them to get a correct overall result. Fortunately, linking the slices is no worse than a single bit, which in the case of addition represents the carry bit. So each 4-bit slice has a carry-in bit and a carry-out bit. (Note that logicals like AND and NOR won't even need this, though if later on you implement left/right shifts, this bit is easily re-purposed).

Carried to an extreme you could use 8 slices of 1-bit each. It's useful to think about the 1-bit slices, because it makes it easier to think about an approach that scales back up to larger slices. So with a 1-bit slice, you have just 7 inputs: the 4 bit function code, a bit from input A, a bit from input B, and a carry-in bit. You also have just two outputs: function out, and carry out. So now you can write the two output functions in terms of just 7 inputs, which is within the realm of human ability to reasonably reduce. You'll end up with a handful of gates that won't necessarily always compute all the functions, but it doesn't matter what happens within the slice, only that it produces the correct result when viewed from outside.

Now you can go a couple of ways. One way is to simply use 8 of these 1-bit slices and you're done. Another way is to make larger slices and then use those. Going from 1-bit to 2-bits, the equations go from 7 inputs to 9, and 4-bits will require functions of 13 inputs. It's not necessarily easy, but will give more compact results than the compute-everything-then-mux approach. Besides, if you look at the internals of a 74181 4-bit ALU slice, you won't see a mux in there.

Electronic – Why does the ALU design delay outputting the results for two clock cycles since input of valid data

If you want immediate results from your ALU, then don't use a clocked process at all:

module alu (
  input [7:0] a,
  input [7:0] b,
  input [3:0] opcode,
  output reg [7:0] y
);

  /* Decode the instruction */
  always @* begin
    case (opcode)
      4'h00 /* OR */:   y <= a | b;
      4'h01 /* AND */:   y <= a & b;
      4'h02 /* NOTA */:   y <= ~a;
      4'h03 /* XOR */:   y <= a ^ b;
      4'h04 /* ADD */:   y <= a + b;
      4'h05 /* SUB */:   y <= a - b;
    endcase
  end

endmodule

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Related Solutions

Electronic – How are various functions (eg. add, subtract, and, etc) implemented in ALU

Electronic – Why does the ALU design delay outputting the results for two clock cycles since input of valid data

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