Electronic – Does an SAR ADC discharge the sample capacitor

DAC error? : You say the scope trace is displaying the Arduino's ADC input values BUT you are apparently displaying an analog signal. I assume there is a DAC of some sort in the process to convert the ADC readings back to analog.
The trace gives the appearance of a DAC with a massive error in a mid level bit. eg address bit A2 of the DAC may have a resistor value that is say 10 times too small.

Test: Turn the pot VERY slowly, do the gross steps vanish?
ie do you get a smoothly descending level.
If the level steps down like that at any sweep speed you probably have a bit based error post ADC.
Or, just possibly a microcontroller with a bit error in the IC's DAC hardware (less likely) .

ADC speed: Failing the above -

General web feel is that you can do better than what you are seeing.
If that pot sweep is in say 0.1 second then your gross step rate is about 10 mS.
HOWEVER- there seem to be small declining steps on your waveform - perhaops 10 per gross step, for a ministep of say 1 mS.
Even that is longer than you'd reasonably expect.

This discussion suggests 10's f kHz. - 77 kHz is mentioned.

Arduino based scope gives an idea of speed expected.

Energy monitor using ADC again, a guide.

Useful

The rise/fall times are not that critical, no. As shown in the data sheet for the device you reference:

Referring to Figure 33, the clock signal alternatively switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle.

So it is not how fast it switches from LOW to HIGH or HIGH to LOW, but how long it remains in that steady state, and how stable your signal is during that state.

Basically, when the clock is HIGH the SHA capacitor is "reading" the analogue signal. When the clock is LOW the SHA capacitor is isolated from the analogue signal, and its voltage is presented to the sampling pipelines for conversion.

Obviously you want to read the value from that capacitor before it decays too much, so an overly huge fall time could be detrimental, but in general the rise and fall times are dwarfed by the required minimum level times (6.2ns to 15ns depending on model). There is no stated maximum time, only a minimum sample rate of 1MSPS, so a maximum clock period of 1µs, or a rise + hold or fall + hold maximum time of 500ns (with the previously stated minimum hold time) by my calculations.

The SHA capacitor effectively looks a little like a low-pass filter, with a time constant equal to the SHA charge time. For one of the devices that is 6.2ns, but others are as much as 15ns.

So the value in the SHA capacitor is effectively like a weighted rolling average of the past 6.2ns of voltages, and the final value is taken at the moment the ADC switches from SAMPLE to HOLD. Therefore you should ensure that the falling edge if the sampling clock occurs during a period where your sampled signal is stable, as it's the end of the sampling period, not the start that gives you your final value.

From your given waveforms, the TRIG signal falls during a trough in the video waveform. The sampled value would therefore be influenced by that trough and the results would be low. The SAMP signal, as the inverse, falls during one of the stable 2.5V periods, and that has been stable for more than 6.2ns, so would give a much more reliable reading of the 2.5V level.