capacitorceramicesrfrequencyimpedance
In most datasheets, I see a typical table which shows that ESR of ceramic capacitor changes with frequency. I understand that impedance of every kind of capacitor must have a minimum due to its inevitable serial inductance. But I don't understand why its ohmic resistance changes as well. Can you please explain this?
The part's datasheet says "Unconditionally Stable with 2.2μF Ceramic", so I think you're good.
(Ceramics have lower ESR than tantalum or aluminum electrolytics.)
Notice the note about increasing the capacitance if you decouple the BYP pin.
My favorite electronics book is "High Speed Digital Design: A Handbook Of Black Magic". I highly recommend this book. It seems expensive, but it is totally worth the money. This book has 12 pages on choosing a bypass cap! The author, Howard Johnson, also teaches some classes with decoupling caps as one of the topics.
Some important things that I've learned over the years, and have been backed up by this book, is that the "standard practices" with decoupling caps are almost always wrong and there is more art than science when it comes to choosing and routing them.
There are lots of calculations that you can do regarding decoupling caps, but much of those are not accurate due to many things. The caps themselves are vary wildly (especially the higher dielectric caps like X7R). The PCB layout changes things greatly (and you'll need to think in 3-D for this one). Temperature and voltage will change the behavior of the caps. A single cap will behave as both a "power supply smoothing cap" and a "AC signal return bypass cap". Etc.
What Johnson did was, after a lot of experimentation, figure out that inductance is the most important factor and it swamps almost every other consideration. So the goal when selecting and placing decoupling caps is to use a lot of physically small caps, with the highest practical value, and route them so the total inductance is as low as possible.
The ideal would be to use lots of 0.1 uF caps in an 0402 package. Place them under the chip on the back side of the PCB. The cap be routed as in the image below. And the vias go directly to the power/ground planes (not to the chip's power pins, as that would usually increase the inductance). If you place the cap under the chip then sometimes you could share the same via without any issues.
The reason why a 0.1 uF cap was chosen is because it is the highest practical in an 0402 package. The reason why 0402 was chosen is because it is the smallest practical size, and you want to use a lot of them to get the effective ESL/ESR down. Of course all bets are off if you have a 2 layer PCB without power and ground planes.
I don't want to belittle the use of the math, that is important, but the complexity of power supply decoupling and AC return paths often makes the math not so practical in the real world. In the real world, a "rule of thumb" really helps. Of the many rules of thumb for this topic, it has only been Howard Johnson that has proven the other rules don't work and provided this better rule. My experimentation and experiences has shown this to be true.
Best Answer
ESR isn't necessarily physically a resistor in series with a capacitor. It's whatever resistor value gives the best approximation to the behavior of the capacitor when it's modeled with a series combination of ideal C, R, and L elements.
Since the resistor is the only one of those elements that causes power to be absorbed by the device, the ESR generally accounts for all the different power loss mechanisms in the device. This includes not just the resistive loss in the leads and terminals, but also the conductive loss in the dielectric.
As to why the ESR(f) curve has that particular shape, the increase at high frequencies is likely actually due to the lead resistance increasing due to skin effect. I can't explain the low frequency increase off the top of my head. My best guess is just that the ESR has to increase to model losses that actually come from a different mechanism (like dielectric loss).