Electronic – Does the source impedance of DC-AC converter always represent losses

This is a fundamental theoretical question about power and efficiency of AC voltage source with very low output impedance, for example, a DC-AC converter; H-bridge converter or class E amplifier.

MY question is:

Does the source impedance of DC-AC converter always represent losses?

To further elaborate the question,

Let's assume the converter to be a pure sinusoidal source with a source impedance of Rs follows. I understand that the source impedance can be a time varying quantity but for the time being, lets assume an equivalent source impedance to be Rs fro a given operating condition.

^{simulate this circuit – Schematic created using CircuitLab}

With this representation, we know when Rs=RL, the maximum power is delivered to the load, and the efficiency become 50%.

My question here is that in actual implementations of such power electronic converter, when the load is optimized to deliver maximum power, is the efficiency always limited to 50%? If not, how it can be explained? Or in other words, Does the source impedance of DC-AC converter always corresponds to losses? I feel I am missing something here.

To elaborate this further,

If now we consider, for example, a class E converter, we know the theoretical maximum efficiency is 100%, in practical implementations, it can easily be above 90%. But highest efficiency is achieved not at the impedance matched condition and I understand that it is not a usual practice to operate at matched condition for such scenario, however, this is for theoretical understanding of such operating condition.

For example, the following figure is from this IEEE paper, efficiency doesn't seem to be less than 50% when the maximum power is delivered to the load.

Additional explanation:

Even if we assume load resistance is not a fixed value (it can be a variable w.r.t with load, and also, it can be a time varying quantity depending on switching transients) we can consider an equivalent source impedance when the output power is maximum. For example, in the above paper, lets approximate power is maximized at 4.5ohm (say, power is maximized when the normalized resistance is around 0.5 in the above graph), then we can deduce that the source impedance seen by the load is close to 4.5ohm. If we consider only this particular operating point, what represents this source impedance (I stress, it can be an equivalent one, or, may even be a time averaged one)?

In adiition, if we can agree that the source impedance is close to 4.5ohm then does the source incur losses corresponding to a 4.5ohm? Then, as the answer by @Neil_UK suggests, should the efficiency be always less then 50% at maximum power delivery condition?

I used this particular reference and numbers to clarify the question. My question is not necessarily limited to this particular converter or class E topology. It is a general to DC-AC converters. I could not find any good reference which discusses this issue?

Or, in another way, is it completely incorrect trying to model a low impedance DC/AC converter (assuming high Q, and load current is fairly sinusoidal) with this model.