I recently bought a ZYBO FPGA board only to find out that there are exactly six regular single-ended GPIO lines wired to the FPGA. In contrast to that, 18 differential lines are available. The board's reference manual says that single-ended communication over the differential lines will work, but has "significant crosstalk". Grounding one line of the differential pair is suggested in this case, but this will obviously negate the whole purpose of having more single-ended IO lines.
So, what exactly is "significant" crosstalk? How fast would I be able to communicate (single-ended)? Would high-speed I2C work well? 2mbit SPI? What about a 25 MHz parallel data transfer? Can anything else be done to avoid or correct for crosstalk?
Best Answer
Although the lines are routed as differential pairs, it's not necessarily a killer to your kind of application. The amount of crosstalk is actually still likely to be quite small, as diffpairs are often routed closer to the groundplane than to each other. It's not like they are a twisted wire with no shield, where the signals are effectively much better coupled to each other. And the traces are likely to be relatively short I imagine (if you are contemplating parallel transmission).
I would suggest you could happily set up a 25MHz parallel bus, with a series-terminated clock to signal the device at the far end to latch the data. Drive the data on one edge, latch it on the opposite edge, you'll have 20ns of time for crosstalk and reflections to settle out). You could drive the negative side of the clock driver to '0' and place it away from the databus to keep that signal as clean as possible. It doesn't sound that different from how we used to route asynchronous SRAM databusses (all the wires run very close together with an edge triggered write-enable line) and that used to work fine :)