Electronic – DVI-D Single Link to FPGA


I'm using LatticeXP2 family FPGA. DVI-D Single link operating at 720p is connected to FPGA. I somehow need to read RGB and XY coordinates of pixels. I know I need TMDS decoder, but I'm not sure how to write that and some sort of clock sync in VHDL/Verilog.

I know there are dedicated chips designed to do that, but I can't afford extra cost to the board.

Best Answer

You will really want to consider using a dedicated DVI or HDMI receiver chip if you need to use the lattice XP2 family. (Both DVI and HDMI use the TMDS protocol.) Alternatively, you could use an FPGA with a built in TMDS receiver, such as the Spartan-6. I did not see any indication on the Lattice web site that XP2 has TMDS capability.

Building a TMDS receiver requires some complex clock/data recovery (CDR) capability, as well as fast deserializers and a good bit of decoding logic. Doing this on your own would be non-trivial. The PLLs and/or DLLs used for CDR in TMDS receivers are typically customized to be a good match with the TMDS protocol and TMDS transmitters. A "generic" PLL on a FPGA may not be a good match for TMDS CDR.