Electronic – electronic switch, understanding on-resistance measurements

analogswitches

I'm trying to understand from the datasheet, how much on-resistance I will get from this electronic switch:

DG411

datasheet: https://datasheets.maximintegrated.com/en/ds/DG411-DG413.pdf

given this conditions:

  • bipolar power supply +/-10V

  • logic 1 = +10V, logic 0 = 0V

  • signal to be switched: AC signal up to +/-7.5V, so quite close to rail voltage.

I'm asking since, as far as I know, on those switches the on-resistance should raise as the voltage to be switched get close to the rail voltage.

I'm not an engineer, and try to read the datasheet, this is what I may have understood:

  • "guaranteed on-resistance flatness over the signal range (Δ4Ω max)"

does this mean that even if the signal raise up, the on-resistance will not vary more than 4Ω?

  • "Low RDS(ON) (35Ω max)"

does this mean the in the worst case, 35Ω will be the maximum on-resistance?

The, watching some graphs at page 5, I'm a bit confused.
I think the most important graph for my doubts is the first one, "ON-RESISTANCE vs. VD AND POWER-SUPPLY VOLTAGE"

I guess I should check the B line (+/-10V), and it looks like the on-resistance in my situation will be something in the range of 27Ω to 33Ω (not considering temperature)

but what is VD?

by the way, I don't need low Ω or precise on-resistance measurement, I'm just trying to understand how to read the datasheet.

Best Answer

Vd seems to indicate the voltage on the D inputs (D1 through D4). Presumably it means the voltage on the Drain of the switch devices.

I'm asking since, as far as I know, on those switches the on-resistance should raise as the voltage to be switched get close to the rail voltage.

You are perfectly correct but the switch is actually made of two devices in parallel - one N-channel FET and one P-channel FET. As the input voltage (Vd) approaches the positive rail the N-channel device does get higher in resistance but the P-channel device gets more bias since its gate is driven by the negative supply rail. The combined resistance tends to be the lowest when the input voltage is mid-way between the rails when both devices have significant bias.

Be careful about reading the data sheet test conditions. They state the supply voltage, input voltage range and temperature. Maximum values should be guaranteed over those ranges.

I can't see what particular conditions the 4 ohm flatness or 35 ohm maximum apples to - it seems to be 45 ohms with 15v supply (-10%) over temperature.

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