I'm trying to get rid of a clkgate timing violation. I have two of them and those are really big violations as you can see in this report:
+--------------------+---------+---------+---------+---------+---------+---------+
| Hold mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):|-157.134 | 0.001 | 0.751 | 0.013 | N/A |-157.134 |
| TNS (ns):|-158.993 | 0.000 | 0.000 | 0.000 | N/A |-158.993 |
| Violating Paths:| 2 | 0 | 0 | 0 | N/A | 2 |
| All Paths:| 2951 | 2792 | 98 | 18 | N/A | 44 |
+--------------------+---------+---------+---------+---------+---------+---------+
Those violations are due to clock gating if I well understood the documentation but there is no more information about the resolution of this type of violation. The violated paths are related to a clock path between a JTAG and a memory.
I tried to use the -clkGateAware option in order to place the cells differently but it didn't help. I already tried to compile multiple time (10x in a row in the hold optimization bloc) but it didn't solve the issue…
What can be the cause of a violation as big as this one ? Is there a simple option that I can use to solve this issue ? Can someone suggest something clever to get rid of this type of clkgate ?
EDIT:
To be clearer: My project is composed of an ARM M0, two SRAM, an HW Accelerator and a SPI. There is also a JTAG slave in order to program the memory with the code for the M0.
All those peripherals are connected to the AHB bus and are working fine. The synthesis is OK without any violation path.
However, when I try to place and route the design, the clock gating occurs in order to reduce the power consumption. This also adds violating paths (two). So my question is more related to Encounter and the optimization commands: Is there something I can do in order to avoid this violated path ?
Best Answer
Simple solution is to slow the clock down. A more complex solution is to use gate types which do not violate the setup time, swap them out if possible. Physically moving them closer in route and place might also be an option.