Electronic – ESD SPI/ISP bus protection

First, you have identified a really annoying part of SPI on the AVR: Connecting SPI slaves will interfere with the proper operation of ICSP.

Second: The SPI bus has MISO, MOSI, and a chip select pin. You can break out the MISO, MOSI and GND pins, and perhaps VCC, plus a different CS pin for each daughter board you want to connect. As long as the CS is not active for the daughter boards, and the daughter board chips do not try to use the bus in master mode, you should be OK.

Third: You can use a buffer chip of some sort (perhaps 74HC125 or similar) with a tri-state function to isolate the ICSP feature from the SPI-talking-to-slaves feature; set the buffer chip up to require a particular pin high to let signals through, and use software to pull that pin high only when your code wants to talk to the slaves, and keep it low after a code reset.

First you should figure out where the problem really is. The description of your setup is confusing, but it seems you are only looking at the SPI bus indirectly thru some firmware that reports things over a UART. There is a lot of opportunity for error in that. SPI busses that are short, on the same board, and above a ground plane pretty much just work. This is no different than other digital signals between chips on the same board. I sounds like you are chasing the wrong problem.

Look at the SPI clock and data lines with a scope. This lets you see what kind of noise there is, and also lets you verify short sequences are really what you think they are. I expect you'll find that you have a bug that is not causing what you think on the SPI bus, or not reporting correctly what is happening on the bus.

Keep in mind that the ENC28J60 has a fairly complicated SPI command set, including a segmented addressing scheme for some of its registers. Start with something simple, like writing some value to a particular register and verifying that you can read it back. Once you have that, it's good to create firmware layers for reading or writing any register, automatically tracking the bank and setting it as needed. Then create another layer for reading/writing PHY registers.

The good news is that the datasheet is well written and complete. I created a driver layer for the ENC28J60 for my TCP/IP stack just from the info in the datasheet.

Added

Another common cause of SPI flakiness is doing things on the wrong edge of the clock. Unfortunately there is no single standard. Look at the datasheet for the chip and the processor carefully to see on what edge of clock each is changing the data and when it is being read. Obviously you want to write on one edge and read on the other. If reading and writing is happening on the same clock edge, then flakiness where things change due to tiny capacitance changes are to be expected.

Again, look at the clock and data on a scope when a known byte is being sent.