To summarize: your board / circuit worked previously, then something caused a component (coil?)to pop, so you swapped out some parts (including the popped component) and your circuit / board no longer works...
Since your MCU can seemingly talk to your ENC28J60 and your ENC28J60 evidently is interacting with the Mag Jack (as evidenced by blinking LEDs), the logical conclusion is that your ENC28J60 is receiving ethernet frames but they are being rejected as invalid (perhaps due to CRC errors or something like that). That would point to something being flaky with components between the Jack and the ENC28J60 or perhaps the external support components for the ENC28J60 (e.g. crystal, capacitors, resistors).
You can get some amount more of diagnostic information out of the ENC28J60 over SPI by reading the status registers, and I would encourage you to do so and report back what you find.
I've used the TEMAC core directly instanciated in logic so I can probably give you some thoughts and answers.
Documentation
Firstly, Xilinx provides a whole host of documents for each of it's IP cores. They also keep documents for different versions of the core, so be careful to pick the right document. A search of the Xilinx support documents came up with this collection of documents:
Xilinx TEMAC Documentation
The main document that you will want to look at is the user manual. It is VERY detailed and should have everything you need to use the core in a project. Saying that, it can be quite hard to work through and fine the information you want.
I'm basing this on v4.5 of the core, I think that's the most recent direct instanciation version (not AXI bus). What cores you can use will depend on how up-to-date your ISE version is, but they don't change of the basics between versions.
The TEMAC v4.5 user manual is at http://www.xilinx.com/support/documentation/ip_documentation/tri_mode_eth_mac_ug138.pdf
Licence
The TEMAC core requires a licence to use. An evaluation licence is free and fully functional, but it stops working after a while
The core can be tested in the target device for a limited time before timing out (ceasing to function) at which time it can be reactivated by reconfiguring the device.
On the Spartan-6 device I used the core on with a 50 MHz clock the core functioned for about 8 hours, but there's no documentation on exactly how the timeout works.
I would get a quote for a licence before you do too much work with the core, it does cost quite a bit of money!
Function
There's a block diagram of the core on page 52 of the document.
This shows you what the TEMAC does in Ethernet jargon, but basically the core interfaces between the user logic and the Ethernet PHY (which drives the actual line signals) on a packet-by-packet basis.
The key to most of your questions is how the "client interface" works. This is the interface to your logic and is well described. Take a look at that chapter to see what the input and output data from the interface is like.
Answers
To answer your specific questions:
How do I know the MAC address of the board?
The TEMAC takes in the MAC address you give it and uses that, so you'll have to provide it from somewhere. Many development boards provide a MAC address EEPROM chip which has a unique address stored in it for you to read and use. If you don't have a MAC address available on the board itself, you can hard code one, but beware that this is kind of against the rules and could possibly cause a problem if another device on your network happens to have that address. One fairly elegant solution is to find an old Ethernet device that you don't use any more and just use it's address for testing.
And once the Temac core is instantiated, will all the data processing be done by it?
No, not really. The receiver and transmitter interfaces work at an individual Ethernet packet level, so your logic must provide individual packets. This is layer 2 on the OSI model. You'll have to create other logic or use another core to handle any higher-level protocols that you want to use (such as TCP or UDP).
I've used this core to make a system work, including writing my own modules to interface with the client interface, and am happy to answer any other questions. Unfortunately my code is owned by the company I work for, but I can talk about it in general.
Best Answer
The connector has only two GND pins.
For better signal integrity you'd need GND lines on both sides of the clock line "OSCIN" (which is actually an output from the PHY module), and probably a few more GND lines to reduce emissions. On this pinout there will be some crosstalk between clock and nearby signal lines.
Also there is only one clock line, running at 50MHz (20ns cycle), it is output by the PHY.
When the PHY transmits data it will be automatically aligned with the clock, and if propagation delays are well matched then RX_Data will reach the MAC with proper timings relative to the clock.
However, when the MAC transmits, it does so according to the clock it receives from the PHY, so these signals will reach the PHY with a delay depending on propagation time (ie, cable length).
The PHY has 10ns data setup time to clock which leaves very little margin with a cycle time of 20ns. So I don't think you'll be able to use a flat cable due to propagation delay.