Electronic – External Code Execution on ARM Cortex M

Once again, it seems I did not utilize google enough.

Section 10.6.7 of the given datasheet also described on this ARM information center page describes the Exception entry and return process.

So the answer to my question is that faulting instruction address resides on the stack at an offset of +0x18 after entering the exception handler.

The behavior of the core does depend on the implementation. The Flash is not integral to the ARM core, and as such, every vendor implements it differently. Typically, during the erase/write process one would execute from RAM, and execution should not be affected.

On the STM32, I believe reads from flash stall while erase/write cycles are ongoing. This would cause the core's execution to stall until the operation completes. With some of the flash configurations, I believe you can continue to execute/read flash and it will only stall when you access the part of the flash that you are eraseing/programming.

I've used other Cortex M's where you must execute from RAM while modifying flash contents otherwise you will encounter a bus fault (and likely a system crash if your bus fault/hard fault handlers are in flash). Some micros with large amounts of flash implement it as two independent flash arrays, and these typically allow for full access to one bank while operating on the other.

You would need to refer to the documentation for your specific part to see the limitations of execution while modifying flash contents.