Electronic – Fastest way to toggle a bit in ASM

What you are doing wrong is making instruction-level assumptions about compiled code. If you want to test the execution speed of instructions, you need to write a known loop in assembler. For example:

loop:
         btg     LATA, #6
         bra     loop

Next you carefully count how many cycles in one full RA6 output cycle. From the datasheet or programmers reference manual you can see tgat BTG takes one instruction cycle and BRA two. Each loop iteration therefore takes 3 cycles, and it takes two iterations for one complete cycle of RA6, so RA6 should toggle at 1/6 the instruction rate, or Fcy/6 using symbols from the Microchip documentation.

Now check whether that part uses 2 or 4 clocks per instruction cycle. Let's say this one uses 2, so now the RA6 frequency is Fosc/12.

Next you have to go thru the config settings and see exactly how the oscillator is derived. It can get pretty complicated on some of the newer parts. Many of them have additional clock chain state that can be adjusted at run time, so you have to look at the code too, not just the config settings. There can be various clock taps, dividers, and usually a PLL that is a multiplier but also usually with its on set of dividers. Eventually you should be able to start at your crystal frequency or the internal oscillator frequency if you're using that, follow thru the whole clock chain, determine what the instruction clock rate is, then divde that by 6 to get the RA6 frequency.

Are you running code from RAM or from flash? ARM processors that run code from flash often require wait states in at least some circumstances; such processors often include hardware which can eliminate most of the wait states in common code, but such hardware may be as simple as a single-line buffer which allows an access to the same line of flash as the previous access to avoid the wait state. If the branch target is the last word of a flash line, then the flash would require two or three cycles to fetch that word, and two or three cycles to fetch the following word. If one of the cycles is performed concurrently with some other CPU operation, that would leave a three-cycle penalty.