Electronic – FET H-bridge has slow convergence for the last 10% of output voltage: why? (DRV8874)

integrated-circuit

I have a board with 9x DRV8874, as described in another unrelated thread there.

The driver switches fast to 90% of VM when ON (0V when OFF) then converges slowly to the final value (time constant~=100us). When the PWM frequency is increased (but still <40kHz specified), the convergence flattens to an average value which deceively resembles bipolar transistors VCEsat varying with duty cycles. The average voltage applied to the load therefore depends on the duty cycle, which cannot be calibrated easily.

Some snaps of the OUT1 voltage (no load connected, measured straight at the IC pins):

Low PWM freq

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Zoom on top

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Nominal PWM freq

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High-ish freq (sorry, other duty cycle)

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And here is how the average voltage varies not linearly with the duty cycle (nominal freq, CH1 is the motor supply, both cursors are set where OUT ends up being at the beginning and the end of the cycle). Notice how the OFF and ON voltages go up with increasing duty cycles.
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I think I managed to model this behaviour using the following model. Vs0 is a constant voltage change when switching, so Vs is shifted up by as much as the voltage at the end of the exponential decay. I'm calculating deltaV and deltaVs for each infinitesimal change in duty cycle and I animated a plot changing the duty cycles, and I have a matching behaviour. Does that help locating the cause?
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(Erratum: k is supposed to be k+1 on the second PWM cycle)

When a load of 12Ohm is connected these figures barely change (drop due to RdsON).

Where does this come from and how can I remedy to it?

Datasheet: https://www.ti.com/lit/pdf/slvsf66

Best Answer

What I am seeing is reverse "droop" caused by un-calibrated oscilloscope probes, or a similar capacitive load at the driver IC (not likely). Could you please verify calibration of your probes, in that they have the square tops and bottoms of a clean square wave. I see no place where else where capacitance, acting to over-dampen the edges of the signal, could happen. Outside of over-dampened snubbers on MOSFET drains or un-calibrated probes, I have not seen this before.

Under-dampened probes and snubbers cause a rising front edge. With little to no dampening you get a leading edge spike, then a fast decaying ring-wave. Please advise what you find after calibrating your probes and testing driver output again.

I am going to study this driver IC to look for bias issues. None found.

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