Electronic – FIFO in ethernet module

Two options:

1. Either You need 23 times faster clock and read the data with that clock.
2. Read FIFO using the same sequential reading method, but burst all the data to output after the data is read. This will result in 23 times larger data burst because of 23 times larger data bus.

The basic answer is that you can do whatever communication you want to do.

Every chip which has an ethernet component to it can do simple phy-to-phy communication (i.e. layer 1 if we're talking about the OSI model), and unless your chip has a built-in IP stack or AX.25 layer or some other type of level-2/3 (i.e. data/network abstraction) layer baked into the silicon, this is what you will have to use.

The hardware is capable of doing some part of the ethernet protocol, whether this is 10BASE-T, 100BASE-T or whatever, and if you add an IP-layer your software stack will utilize that functionality. You can use that functionality directly!

Most people choose to put some sort of IP layer with TCP or UDP communications because this helps hide some of the complexity, and makes the code work the same way on their computer as it does on the chip. It also means that things like putting an ethernet switch in the middle of multiple circuits will work, and many other niceties that comes with using a professionally developed standard that a lot of people have thought about and tested. You don't have to do this if you don't want to, and it will save you a lot of complexity and processing power if all you're doing is sending simpled sequential messages from one circuit to another though.

I agree with @Spoon though, in that I think you should pick a different protocol if you're using simple point-to-point communication. If there a reason you're not using RS-485, RS-232, I²C, or some similar simple serial protocol? A lot of those will likely be easier than using ethernet.

Good luck!