I'm looking for the FET (JFET, MOSFET and other more advanced variants like Heterojunctions) that has the lowest channel modulation or perhaps among the lowest. Now, before anybody argues if other FETs do have it, then at least JFETs also have it, as some sources will say. It's just that it's most pronounced with MOSFETs (along with other short channel effects), seeing they are scaled way down with the CMOS process.
But, as most of you know, it's not a parameter listed in datasheets. So I'm trying to resort to deriving by other parameters. Although I've ran into some problems. \$R_{OUT}\$ or \$R_{DS_{ON}}\$ is calculated as:
$$R_{OUT} = \frac{1 + λV_{DS}}{λI_{D}}$$
I believe that to more accurately derive \$λ\$ it ought to be (assuming \$λ\$ is a constant, giving a linear growth for the channel length modulation — a simplified model):
$$R_{DS_{ON}} = \frac{1 + λV_{DS_{SAT}}}{λI_{D_{SAT}}}$$
$$λ = \frac{1}{R_{DS_{ON}}I_{D_{SAT}} – V_{DS_{SAT}}}$$
where pairs {\$V_{DS_{SAT}}\$, \$I_{D_{SAT}}\$} are any point past the beginning of saturation region where channel modulations has started to take effect.
Now, in the datasheet, typically, \$R_{DS_{ON}}\$ is listed with \$V_{GS}\$ and \$I_{D}\$ given. It's implied for the most part that all parameters are tested at some point in saturation. So, some \$V_{DS_{SAT}}\$ is \$V_{DS_{SAT}} ≥ V_{GS}\$. So we can have
$$V_{DS_{SAT}} = V_{GS} \quad (given) $$ $$I_{D_{SAT}} = I_{D_{RDSON}} \quad (given)$$
Though, of course, we are simplifying and linearizing clm, so we need a \$(V_{DS_{SAT}}\$, \$I_{D_{SAT}})\$ that is well within the clm effect and not at what probably is just the meeting point of the peak of the linear region and the start of saturation region. So that's the technical problem.
Other than the last paragraph, what other problem do you guys think there is?
EDIT:
I meant:
$$V_{DS_{SAT}} = V_{GS} \quad (given) + V_{extra}$$
So in the more ideal case that \$V_{DS_{SAT}}\$, under which everything is tested, it is well within the clm taking effect, we need the offset \$V_{extra}\$.
EDIT:
corrected the formula to \$R_{OUT}\$. My mistake.
Best Answer
Long ago I went through a similar search for BJTs with the highest Early voltage. My finding was that higher voltage devices had a higher Early voltage. Turns out there is a fundamental reason for this that I won't go into.
Instead of using a high voltage device, I switched to a cascode design, which greatly increased the output impedance.
It is possible to stack more transistors into the cascode and increase the output impedance even more.
With FETs, a dual-gate device does the same thing as a cascode, but in one device.