I had this problem in my digital electronics final. I want to know how to solve this, although I'm going to use different values since I don't remember the exact values from the test.. I'm going to write out my solution as well, but I only did this solution because I had seen similar problems, I don't understand the reasoning or even know if it's correct. My goal is to understand this, as I feel like I understood every other part of the course pretty well. But electronics has been very challenging to me, as I'm a computer engineer.
Problem information:
The following sketch shows the circuit for a dynamic RAM cell.
The transistor is an NMOS. \$V_{DD} = V_{WL} = 3V, V_T = 1V\$ When there is a read operation, BL is pre-charged to \$\frac{V_{DD}}{2}\$. The bit line capacitance \$C_{BL} = 0.1pF\$. Determine the minimum value for the cell capacitance \$C_C\$ so that during a read operation the change in voltage in the BL is at least 10mV. Ignore body effect.
My solution:
For logic-1 the voltage in \$C_C\$, \$V_{C_C(1)}\$ would be \$V_{WL} – V_T = 3 – 1 = 2V\$.
For logic-0 the voltage in \$C_C\$, \$V_{C_C(0)}\$ would go down to 0V.
Logic-1:
The professor has used this formula few times, I don't really know the reasoning behind it. When I asked, they said conversation of energy. I guess I just accepted that, because it seems like it'd make sense. Here it is:
\$C_C * V_{C_C(1)} + C_{BL}*V_{C_{BL}(1)} = V_f * (C_C + C_{BL})\$.
So we know all these values, we can plug em in:
\$C_C * 2V + 0.1pF * 1.5V = 1.51V * (C_C + 0.1pF)\$
And we solve for \$C_C\$, so \$C_C = 2.04fF\$
Logic-0:
Using the same formula as before:
\$C_C * V_{C_C(0)} + C_{BL}*V_{C_{BL}(0)} = V_f * (C_C + C_{BL})\$.
We plug in our known values:
\$C_C * 0V + 0.1pF * 1.5V = 1.49V * (C_C + 0.1pF)\$
We find that \$C_C = 0.67fF\$.
Conclusion:
When we have logic-1 we need a cell capacitance \$C_C = 2.04fF\$, and when we have a logic-0 we need a cell capacitance \$C_C = 0.67fF\$, in order to have a \$\Delta V_{BL} = 10mV\$. If we made the logic-0 \$C_C\$ any bigger, it would just cause the \$\Delta V_{BL}\$ to be higher, which would be fine. If we made the logic-1 \$C_C\$ any smaller, then the \$\Delta V_{BL}\$ would be less than 10mV.
Therefore, the answer is \$C_C = 2.04fF\$.
Is this correct?
Best Answer
Yes, it is correct. I did not check the numbers, but the procedure is correct.
To help you understand what you are doing, here is an explanation of the formula. When you perform a read operation, you turn on the NMOS. This means that you somehow shortcircuit Cc and the bit line. These are two capacitors charged at different voltages, so when you connect them a redistribution of charges takes place. The formula that you are using is actually about charge conservation, and not energy conservation. The charge Q stored in a capacitor equals its capacity times the voltage across its leads: $$ Q\ =\ C \cdot V$$ So what you are doing is just match the charge present before the connection, and the charge present after, keeping in mind that after the short circuit we can model the Cc-BL capacitor as the parallel of the two. $$Q_i = Q_f \\ C_C\cdot V_{C_C}+C_{BL}\cdot V_{C_{BL}} = C_{tot}\cdot V_f$$ The final voltage must be greater than \$V_{C_{BL}}+\Delta V\$ if we had a high level and less than \$V_{C_{BL}}-\Delta V\$ if we had a low level. Using this condition will lead to two separate equations that are easily solved: $$ C_{C(1)} \ge \frac{C_{BL}\cdot \Delta V}{V_{C_C(1)}-V_{BL}- \Delta V} \\ C_{C(0)} \ge \frac{-C_{BL}\cdot \Delta V}{V_{C_C(0)}-V_{BL}+ \Delta V} $$
The higher value of capacitance is the one you are looking for.