Madmanguruman and David Tweed are probably on the right track here.
Here is a scenario:
When the circuit starts the synchronous FET (T2) will be on. It has to be this way because there is no bias voltage for the high side drive for T1 except through T2. So, T2 sinks current from the battery through the inductor. Then finally T2 turns off. It doesn't matter if T1 turns on or not, the inductor dumps current back through T1 (or its body diode). The current has to go some place. SMPS are 1 quadrant devices (almost always), so the Laptop supply sinks nothing. The current can only go into C5 and Vcc of the IR2104, which has a max supply voltage rating of 25V. Boom.
Yes, this sort of thing comes up regularly. We have settled on a system that works pretty well for small boards. Here is one example:
The top part is hinged at back and swings up. You then place the board to test in the cradle for that purpose:
What you can't see in that picture are the pogo pins that stick up from the tester under the board. When the lid comes down, it presses on the board at carefully selected points. This compresses the pogo pins a bit so that they make reliable contact. Pads were designed onto the bottom of the board under test for just this purpose.
When the lid is lowered, a little latch swings over part of the lid arm:
This does two things. First, it locks the lid in place keeping the pogo pins compressed a little. Second, it releases pressure on a microswitch. This switch is wired to the processor on the tester. It is used as the signal to start a new test.
The general design is canned, but the details are not. The pogo pins are held in place by the thick plastic piece screwed to the test board. This has holes in it matching thru-hole pads in the test board below. The pogo pins holders are placed into the holes in the plastic from above. A small piece of each holder protrudes thru the pad in the tester board, and is then soldered from the bottom.
This is a convenient way to make electrical connections to the pogo pins. They are just single-pad thru-hole components from the tester board's point of view.
The tester then contains whatever circuitry you need to test the board. This usually includes controllable power supplies with voltage and current signals going into the control micro. In this example, part of the test procedure was performed on a PC, and the tester communicated with the PC via USB. A PIC 18 was used to run the tester.
The test procedure includes programming a PIC in this case. For that we usually start with our USBProg PIC programmer circuit, but use a larger PIC so that there are a bunch of pins available for the test function. We even added 16 reserved commands to the official PIC programmer protocol to support testers that are USBProgs with added features.
Once we have the test circuit board mechanical details, we send them off to a mechanical engineer that we work with. He then takes the general tester design and adds the details for that specific tester. He designs the bottom plastic part, the lid, the exact mounting holes, the plexiglass top cover, and the like. We've done this a few times, and have the process down to a few $1000, usually for three tester units. Of course the cost of developing the tester firmware and host software is the biggest expense.
In general, figure the tester is roughly of the same level of complexity as the thing it is testing. You need to alert management of this early so that they know it's coming. All too often they think you're done with a project when you get the first prototype working on the bench.
Even if you've warned them all along, you still often find inexperienced managers that don't want to take 2 months to develop a proper tester, after having just spent 4 months developing a product that needs testing. The best solution I've found is to just include a tester in the schedule and budget from the first day, although even that doesn't always work. Particularly inexperienced low level managers have a great capacity for being penny-wise and pound-foolish.
Best Answer
What's the purpose of the capacitor on the output of gate driver IC, and where did you found that 100 ohm gate resistors are good choice.
Next, why the gate driver is so far away from MOSFETs? Also, gate traces may be too thick, the inductance is increased, however you didn't mention the PWM frequency, if enough low this won't be an issue.
I don't see that MOSFETs have both drain and source connected on PCB layout.
EDIT:
The absolute maimum rating for U3 is 20V, while datasheet says that the working voltage is 4.5 to 18V, therefore you can't use 20V as Vcc.
The cap on the U3 output mentioned on page 10 of its datasheet is used for a test, it simulates the gate capacatance of the MOSFEET, but it is not intended that you mount a capacitor on the output in real project.
The gate resistor is usually very low from 3 to 10 ohm, surely not 100.