There is no concept of 'delimiting' bytes in SPI. The simple fact that 8 bits have been transmitted constitutes a byte, and the ninth bit would be the first bit of the next byte.
In SPI reception begins when the chip select line is lowered (or raised for some chips). The data is then clocked in one bit at a time into a shift register. As each bit arrives the shift register shuffles all the bits down one.
An SPI chip typically has a fixed shift register size, and is not bound by byte sizes. Some have multiples of 8 bits, which is nice, some have 10 bits, some 17 bits, etc.
If you clock in more than the required number of bits the first bits kind of drop off the end of the shift register and are lost, so if you have a 10 bit shift register, and you can only send multiples of 8 bits (which is common with the PIC chips), then if you send the first byte as 6 bits of 0 followed by 2 bits of data, then a second byte of 8 bits of data, the first 6 bits will be discarded as they drop off the end, and the shift register will only contain the last 10 bits.
Addressing modes are basically taking a few extra bits in the SPI data stream and comparing them to a set of pins tied either high or low on the chip. If they match then the data in the shift register should be acted upon. If they don't then it should be discarded.
A number of SPI chips include a pass-through function where you can chain them together, and as data is clocked into the first chip what is at the end of its shift register, and would normally be discarded, is sent to an output pin. This can then go to the input of the next chip thus passing the data down the line from chip to chip. In this case it is critical to make sure your data is packed into a single stream with no bits that you'd normally discard (can be tricky if the chips don't use multiples of 8 bits).
The number of 'wires' in SPI is misleading at best, as it doesn't really tell you how many real wires are needed.
Typically you have:
- Clock
- Chip Select
- Data in
- Data out
Some chips may not have a data out, and they only accept data into them. Some combine the in and the out together, so you have to split them apart somehow - either in software if you can, or in hardware.
If you have both data in and data out, then SPI can work in full duplex mode (but doesn't always) where as you clock data into the shift register, data is also being clocked out for you to read. This isn't often used, as most systems rely on a command being sent before a response can occur. There is sometimes another line to signal when the data has finished being sent to the SPI device and the response should be sent. More often, though, it happens when a certain number of bits have been received, or a certain combination of bits. It is common to pad the start of a transmission with 0 then signal the device to start receiving with a start bit.
There are many ways of doing it, and no one ever seems to do the same thing as anyone else - or even as themselves sometimes.
SPI defines how the data is transferred, not how the data is formed.
Some types of non-volatile memory device use error-correcting logic which adds an extra few bits to each programmable chunk (e.g. 5 bits per 16, 6 per 32, 7 per 64, 8 per 128, etc.) Generally the error correction code is chosen so that all bits blank is a valid representation; in some cases, but not all, it may also be chosen such that all bits programmed is also a valid combination. For simplicity, I'll assume a code with which guards each group of 4 bits with 3 guard bits. Compute the three guard bits guard bit as being the xor of either data bits 0+1+3, 0+2+3, or 1+2+3. I'll also assume that a blank word is zero.
The 16 possible code values are thus
3210 ABC 3210 ABC 3210 ABC 3210 ABC
0000 000 0100 011 1000 111 1100 100
0001 110 0101 101 1001 001 1100 010
0010 101 0110 110 1010 010 1110 001
0011 011 0111 000 1011 100 1111 111
When a memory nybble is read, the system can see what bits ABC should be according to the table. If one of the seven bits in the word is misread, the combination of ABC bits that don't match the computed value will indicate which bit was wrong.
Suppose a memory system used the 16-bit code shown above, and one wanted to overwrite a byte value of 1110 (ECC bits 001) with a value of 1000 (ECC bits should be 111). The net effect would be that the system would write 1000 with ECC bits of 001. When the data is read back, the system would see that for a value of 1000, the ECC bits should be 111 but are instead 001. The fact that bits A and B are wrong means bit 0 of the data was wrong and should be flipped; the system would thus read the value as 1001 (whose ECC is correctly 001).
In most cases, there should be enough flexibility in the design of an error-correcting code to permit both all-bits-clear and all-bits-set to be regarded as valid combinations. Some systems do not do so, however. If an error-correcting code would require an all-bits-programmed word to have two or more of the ECC bits blank, then an attempt to obliterate a word which has those bits programmed would likely visibly fail; attempts to program many other values would likely yield a state which was only one bit error away from failure rather than two.
I really wish memory designers would allow for data to be obliterated even if they don't allow most other overwriting patterns. Especially with NAND flash, it would make some operations a lot easier.
Best Answer
Yes, after any erase, you can use any number of separate operations to write data (changing bits from 1 to 0) before the next erase operation.
You can even rewrite a previously-written location, as long as you are only clearing more bits. This can be handy for maintaining things like allocation bitmaps.