Electronic – For-Loop and repeat synthesis

verilog

We all know that the For-loop and Repeat are synthesizable, they get converted to blocks, for example:

for (idx = 0; idx < 4; idx=idx+1) begin
a = a + b[idx];
c = c + 2;     //You can change more than one variable in a for loop
end

In that example, the resulting hardware will be a chain of adders, summing the values from four array indices.

So my question is what if the For loop iterates over a huge number let's say 10000 ? Will it create a 10000 adders ?!

Best Answer

Yes, but synthesis tools have a 'maximum loop' value at which they stop.

You can change the value but the default seems to be set rather high.
If you get a warning it is very likely that you have done something wrong.

Related Solutions

Electronic – Unsigned addition overflow and synthesis

Synthesis will give you a truncated but otherwise accurate result, assuming all regs/wires mentioned are unsigned (i.e. not declared with reg signed). The map tooling will probably warn about a 'carry' line having 'no load', if you can find it in the logs. You might be able to suppress the warning with an explicit bit select on the result or a mask:

a <= (b + c) & 0x7;

Electronic – Memory modelling and Memory module in Verilog synthesis

I am not sure why you need a special option, the use of memories are pretty standard for use inside modules. Unless you are trying to imply a special low area/power cell similar to a ram.

For a standard memory it is just the same as having multiple regs. memory does not imply RAM the same way reg does not automatically imply flip-flop.

The 'memory.list' is a plain text file which contains the values which you want to load in to the memory, this is not required if you just wanted to reset the memory and have every element at 0.

memory.list should look like :

//Comments are allowed 
1100_1100   // This is first address i.e 8'h00
1010_1010   // This is second address i.e 8'h01
@ 55        // Jump to new address 8'h55
0101_1010   // This is address 8'h55
0110_1001   // This is address 8'h56

The use of the file would then follow :

module  memory();
  reg [7:0] my_memory [0:255];

  initial begin
    $readmemh("memory.list", my_memory);
  end
endmodule

alternatively :

module  memory();
  reg [7:0] my_memory [0:255];
  integer i;

  initial begin
    for( i=0; i<256; i=i+1) //Can be statically unrolled
      my_memory[i] = 8'h00 ;
  end
endmodule

If using as a bank of flip-flops with async-reset:

module  memory(
  input clk,
  input rst_n,
  input [7:0] addr_wr,
  input [7:0] data_wr
);
  reg [7:0] my_memory [0:255];
  integer i;

  always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
      for( i=0; i<256; i=i+1) //Can be statically unrolled
        my_memory[i]  <= 8'h00 ;
    end
    else begin
      my_memory[addr_wr] <= data_wr ;
    end
  end
endmodule

Best Answer

Related Solutions

Electronic – Unsigned addition overflow and synthesis

Electronic – Memory modelling and Memory module in Verilog synthesis

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