I would not use an FPGA.
You mention you have no experience with FPGA's, and yet you are interested in doing digital signal processing on an FPGA... numerical manipulation + signal processing are difficult enough to get right on a computer/DSP/microprocessor, where the programming tools are conventional programming. It seems to me that using a digital signal processing project for a first FPGA project is likely a recipe for frustration.
If you want to learn FPGAs, try doing something more suited to the development tools, like state machines or communications packet processing.
For a DSP project like what you've described, I'd recommend a DSP or a Cypress PSOC or an Analog Devices Microconverter (=microcontroller with ADC+DAC builtin) instead.
(full disclosure, which provides some context for my advice: I do not use FPGAs myself. I have used programmable logic = PLDs on rare occasions. My officemate does use FPGAs frequently, and I've seen enough VHDL/Verilog code looking over his shoulder to know that it is well suited for bit manipulations. He is a seasoned engineer with lots of experience with FPGAs; in a recent conversation with him where he was doing some fairly simple math on integers with different bit widths, I told him he needed to do sign-extending on the shorter bit width number in order to subtract it properly, and he got this look on his face, like "oh man, I don't want to have to do sign extension..." Adding and subtracting is not very hard in an FPGA. Beyond addition and subtraction, you really need to know the tools and libraries. And floating-point processing??!?!!??!?!!?)
Best Answer
FPGAs have pre-placed and pre-routed clock trees in order to deliver high fanout clocks to large parts of the FPGA with low skew. This is a buffered clock, and it's the normal way of using a clock in a design. These nets are driven by one of the clock buffer primitives (BUFG, BUFGMUX, BUFGCE, etc.). There are a limited number of global buffered clocks, but there are also regional clocks that can be used for smaller synchronous blocks.
An unbuffered clock would be a clock that is routed through the fabric, the same way design nets are routed. These nets have lots of delay and should not be used for clocks unless there is a good reason. Using them for clocks will almost certainly lead to hold time violations that the tools may or may not be able to clean up.