Electronic – FPGA SPI slave not working well

fpgaintel-fpgaquartusspivhdl

I'm tring to integrate a SPI Slave in VHDL (opencores)
http://opencores.org/project,spi_master_slave
the idea is to interface a Microcontroller and an FPGA
I'm Using Quartus..

more info:

microcontroller diferent clock 50 MHz i think..
SPI clock frequency is 16Mhz
SPI VHDL core clock @ 100 Mhz
I've made an endurance test writing and reading some registers .. no errors with spi

the problem :

when I try to integrate the VHDL SPI to the rest of my VHDL application (also 100mhz)… the circuit becomes a little "unstable"

some symptoms:

sometimes in some registers there are bits I didnt write by spi, making the vhdl application to act inexpectecly..
When adding signaltap probes , the behabior of the vhdl changes a little..

questions:

Do I need to use timequest for the SPI CORE , to add timeconstraingts to SPI input pins?
Do I have metastability ?

Best Answer

Your assumption that you have metastability problem seems correct. I did only a survey of the spi slave code, and here what I found:

The spi clock is used as is, i.e. it requires a clock buffer.
The data you read from the spi core is not resynchronized to the 100MHz clock, it is on the spi clk domain.
The data valid signal is resynchronized to the 100Mhz clock.

If you read the data continously, you will have metastability since it is not synchronized. The core's designer probably expects you to use data valid to prevent that. I personally think it's a bad design and would use to shallow FIFO to do the deed cleanly.

Furthermore, I'd prefer to do what Brian suggest and just synchronized the spi clk/data to a faster clock (that 100MHz) and do the core logic with that clock. 16MHz to 100MHz will skew the clock edge for your output logic (after resynchronization), but it should be O.K..

As for constraints, 16MHz is very very slow... You don't need constraints, your CPOL/CPHA has to match though, obviously.

Related Solutions

Electronic – DMA completion interrupt not working for slave STM32 SPI

I found the solution. In reference manual of STM32f103xx there is a table (No. 78) clarifying that which DMA channel can be used for which peripheral. According to that table, I had to use DMA1 channel3, while I was using channel6 instead.

VHDL code works well in ModelSim and strange behavior in Altera FPGA

There are several problems in your code:

1)
PRESENT_STATE is not in the sensitivity list of process listen. It should be, otherwise the simulation gives you other results as in hardware.

2) SGN_IN is not an input of your FSM. There is no transition that depends on this signal. Listing signals in the sensitivity list does not promote them to inputs. This list is just for simulators and ignored by synthesis tools.

3) Because you are using SGN_IN in the sensitivity list it seams to work correctly in simulation, but this is just the luck of 2 errors resulting in the correct simulation result :). Your FSM would also transition if SGN_IN is changed to X or L, because the signal changed, but I assume you want to check for 1-0/0-1 transitions, am I right?

listen: process(PRESENT_STATE, SGN_IN) is
begin
  NEXT_STATE <= PRESENT_STATE;
  Y          <= '0';

  case PRESENT_STATE is
    when ST0 =>
      if (SGN_IN = '1') then
        NEXT_STATE <= ST1;
      end if;
    when ST1 =>
      Y <= '1'; 
      if (SGN_IN = '0') then
        NEXT_STATE <= ST0;
      end if;
  end case;
end process listen;

Best Answer

Related Solutions

Electronic – DMA completion interrupt not working for slave STM32 SPI

VHDL code works well in ModelSim and strange behavior in Altera FPGA

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