Electronic – FPGA VGA Buffer. How to read and write


I have an Altera DE2 board and trying to draw sprites. I am having some trouble implementing a screen buffer.

I have a display entity that at a 25 MHZ rate outputs pixels for vga display.

I was hoping to implement a buffer in SDRAM. The original idea was to load pixels the next pixel at a rate of 25 MHZ from the SDRAM. This works, but I can't write pixels to the SDRAM at this rate nor can clear the screen fast enough for each new frame. It takes me 2 clocks to write data and my board operates at 50 MHZ so I have just enough time to do a complete read.

I would assume I'm doing something terribly, terribly wrong. How is such a drawing canvas normally implemented in VHDL?

I closest thing I could find is to use a 2-3-3 (R-G-B) color scheme to retrieve each pixel and write to the canvas ram during the "porch" (blanking) VGA time. This means that at each of the 25mhz clocks I can only update 15% of the screen and I somehow need my circuit the be aware of which 15% it is updating?

I can't figure out how to use double buffering because I can't figure out how to write data to the memory while reading. Is there a way to avoid bit-banging the protocol? How does this guy do it?

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Best Answer

A couple of approaches which may be useful for some styles of display is to divide the display panel into tiles, and

  1. restrict each tile to using a small set of colors, allowing the use of fewer than 8 bits per pixel, or
  2. use a byte or two from each tile to select a location from which to read bitmap data.
The first approach could reduce the rate at which data had to be read from display memory. For example, if one used tiles that were 16x16 and could each have four colors chosen from a set of 256, then without using any extra RAM in the FPGA one could reduce the number of memory reads per 16 pixels to eight (four color values, plus four bytes for the bitmap). If one added 160 bytes' worth of buffering/RAM(*) to the FPGA, one could reduce the number of memory reads per 16 pixels to four, using an extra 160 reads every 16 scan lines to read the next set of tile colors. If one wanted 16 colors per tile, the second approach would require an extra 640 bytes of RAM unless one placed some restrictions on the number of different palettes that could exist on a line.

The second approach would probably increase rather than reduce the total memory bandwidth required to produce a display, but would reduce the amount of memory that would have to be updated to change the display--one could change a byte or two to update an 8x8 or 16x16 area of the screen. Depending upon what you're trying to display, it may be helpful when using this style of approach to use one memory device to hold the tile shapes, and another to hold the tile selection. One might, for example, use a fast 32Kx8 RAM to hold a couple 80x60 tile maps with two bytes per tile. If the FPGA didn't have any buffering, it would have to read one byte every four pixels; even with a 40ns static RAM, that would leave plenty of time for the CPU to update the display (an entire screen would only be 9600 bytes). The memory bandwidth for reading out the tile shapes would be no better than it is now, but that part of memory wouldn't have to be updated.

Incidentally, if one didn't want to add a 32Kx8 RAM but could add add 320 bytes of buffering/RAM(**) to the FPGA, one could use a tile-map approach but have the CPU or DMA feed 160 bytes to the display every 8 scan lines. That would burden the controller somewhat even when nothing on the display was changing, but could simplify the circuitry.

(*) The buffer could be implemented as RAM, or as a sequence of 32 40-bit-long shift registers plus a little control logic.

(**) The buffer could be implemented as two 160-byte RAMs, or as two groups of sixteen 80-bit shift registers.