Electronic – Gate Output as a Switch

digital-logic

I was randomly browsing around some Introduction to circuits websites when I came along this:
enter image description here

The text that went with it is:

Now let us consider what happens when using the output of a chip, such
as the 74HC04, to operate an external device. For example, the circuit
on the right drives an LED. When the gate is HIGH, then there is no
path to GND for cathode of the LED L1. When the gate is LOW, then
output pin 2 is connected to ground, and current flows. Since R3 only
allows 15mA of current to pass, the gate is safe from being
overloaded. Remember that most gates can handle 20mA of current. The
same holds true for most microcontrollers.

Can someone explain how this works (I realize this is probably super newbish to most people)
I understand how logic gates work, that is an OR gate correct? My "assumption" is that since it's an OR gate….when the Input (or 1) is set to low (or zero) it allows current to pass through?….but if thats the case shouldn't it be like….facing the other way. I guess im confused at why the LED is on the output side with Vcc. I guess I just don't understand why the OR gate isn't facing the other way. Im probably being dumb lol

Best Answer

To expand a bit on @Barsmonster's answer, if you look at the CMOS implementation of a gate, there is a "pull-up" network of P-type transistors and a "pull-down" network of N-type transistors. The inverter is the simplest case of such a gate and it looks something like this:

enter image description here

When A (labeled "1" in your diagram) is set to Vss (GND), the P-type transistor turns on (and the N-type transistor turns off), and Q (labeled "2" in your diagram) is effectively connected to Vdd. When A is set to Vdd the N-type transistor turns on (and the P-type transistor turns off), and Q is effectively connected to Vss.

The current limit they are talking about is how much the N-type transistor can sink without burning up.