I am currently working on converting a high level language into an equivalent circuit.. I am able to convert simple expressions like a+b, a.b or a combination of them using gates. But I wanted to know if there's a generic method to implement if-else statement using electronic components such as gates, mux, ff. A simple answer would be to use mux-demux. But that wouldn't solve the following problem(for example)
if(posedge(clock)):
q<=d
The construct for that would be positive edge triggered flip flop. So is there any general way to implement if-else statement?
Any help would be appreciated. Thanks!
Best Answer
For combinational logic,
if
/else
is implemented as a 2:1 multiplexer. In Boolean algebra, this would be:where:
S
is the input fed by theif
condition,A
is the input fed by thethen
subexpression,B
is the input fed by theelse
subexpression, andQ
is the output of the expression.You could theoretically generalize this to include a single clock edge, but it gets a lot more complex and would resemble an FPGA cell when you're done. Basically, if a clock edge were included, you could not have an
else
clause (because it is implicitly "do not change the output"), and any non-edge parts of theif
condition would simply become the clock enable expression. Once the dust settled, you'd be left with a less-clear version of thealways_ff
statement, which you should use instead anyway.Conditions with two or more clock edges are not synthesizable.
EDIT: First, I'm not sure
if(posedge(...))
is synthesizable. In general, you use theposedge(...)
clause in thealways_ff @(...)
line and don't need theposedge()
inside the block.In SystemVerilog, the generic form of a 2:1 multiplexer is an
if
statement. For example:If there's a clock edge, though, you need to use a flip-flop:
Adding an asynchronous reset looks like this:
In this case, RESET is active-high. Note that you only need to say RESET is edge sensitive in the
@()
part. In the rest of the block, RESET will have the level after the edge. Also note that the edge-sensitivities are a list; you can't say "and". (In original Verilog, you separated edge sensitivities with "or", misleading people into thinking "and" could work as well.)