In Razavi's Design of Analog CMOS Integrated Circuits (page 126 in second edition), he presents two variations of the Gilbert cell, one were the control voltage is applied to tail current sources (left) and one where the control voltage is applied to cascode devices (right):
For the version on the left, he says that if \$V_{cont1}-V_{cont2}\$ goes very high, then the current is routed through the diff pair of transistors \$M_1, M_2\$ and the gain is negative. If the differential control voltage goes low, then the tail current is routed through the other diff pair and the gain is positive. This makes sense since it's just two side by side diff pairs whose gains make sense given the definition of the output voltage polarity.
For the gilbert cell on the right, there are the following two situations depending on if the control voltage goes high (left) or low (right):
Here, Razavi says that the left version has positive gain and the right version has negative gain. The output voltage polarity isn't explicitly shown, but I would assume that it should be the same as before since nothing special was said, so left branch is the positive terminal, right branch is the negative terminal. If that were the case, then shouldn't the left version actually have negative gain and right version have positive gain?
Best Answer
View these Gilbert_cell circuits as analog versions of an Exclusive Or gate.
Thus there is a polarity interaction within the circuit.