STM32 GPIO – Resolving GPIO Boundary Address Confusion

gpiomemorystm32

Background

I'm currently digging into STM32L0 series and I stumbled something I couldn't answer.
According the the datasheet page 58 we can see all the peripherals are clumped into a section of 512 MB, now in that section the IOPORT bus resides, this bus handles all the GPIO ports according to page 56.

According to the vendor software each PORT is offset by 0x0000 0400 starting from 0x5000 0000 being PORTA
0x5000 0400 being PORTB and so on..
I tried looking through the compiled memory map and register view, but didn't get any smarter.

Question

Why does each port(A,B,C,D,E,H) have 1 kB allocated, when according to the datasheet/vendor provided SW they only have 11 x 32bit registers associated with them adding up to 44 bytes?

What could this be – Am I completely off ?

typedef struct
{
  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 
  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 
  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 
  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C 
  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 
  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 
  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 
  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C 
  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 
  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 
}GPIO_TypeDef;

Best Answer

Only the manufacturer would know the specific reason to that. But basically, if there is memory space to spare, it does not make much difference how the memory is allocated to peripherals.

But without further knowledge about manufacturer intentions, if you have 512MB of memory addresses allocated for peripherals, it would make sense to divide the area into large enough blocks to ease the memory address decoding.

For example in this case, the whole address range at 0x5000XXXX could be simply forwarded on to the GPIO bus, and then 6 upper bits of XXXX can access a single kilobyte to select which GPIO peripheral is to be accessed, and then the specific GPIO peripheral can use any amount from the low 10 bits to access up to 1 kilobyte of registers. It's just that some other peripherals may need more registers than a few, as GPIO peripherals are quite simple. For example, the USB peripheral has one 2KB range as it has the FIFO memory.

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