I'm not sure why you think BJTs are significantly slower than power MOSFETs; that's certainly not an inherent characteristic. But there's nothing wrong with using FETs if that's what you prefer.
And MOSFET gates do indeed need significant amounts of current, especially if you want to switch them quickly, to charge and discharge the gate capacitance — sometimes up to a few amps! Your 10K gate resistors are going to significantly slow down your transitions. Normally, you'd use resistors of just 100Ω or so in series with the gates, for stability.
If you really want fast switching, you should use special-purpose gate-driver ICs between the PWM output of the MCU and the power MOSFETs. For example, International Rectifier has a wide range of driver chips, and there are versions that handle the details of the high-side drive for the P-channel FETs for you.
Additional:
How fast do you want the FETs to switch? Each time one switches on or off, it's going to dissipate a pulse of energy during the transition, and the shorter you can make this, the better. This pulse, multiplied by the PWM cycle frequency, is one component of the average power the FET needs to dissipate — often the dominant component. Other components include the on-state power (ID2 × RDS(ON) multiplied by the PWM duty cycle) and any energy dumped into the body diode in the off state.
One simple way to model the switching losses is to assume that the instantaneous power is roughly a triangular waveform whose peak is (VCC/2)×(ID/2) and whose base is equal to the transition time TRISE or TFALL. The area of these two triangles is the total switching energy dissipated during each full PWM cycle: (TRISE + TFALL) × VCC × ID / 8. Multiply this by the PWM cycle frequency to get the average switching-loss power.
The main thing that dominates the rise and fall times is how fast you can move the gate charge on and off the gate of the MOSFET. A typical medium-size MOSFET might have a total gate charge on the order of 50-100 nC. If you want to move that charge in, say, 1 µs, you need a gate driver capable of at least 50-100 mA. If you want it to switch twice as fast, you need twice the current.
If we plug in all the numbers for your design, we get: 12V × 3A
× 2µs / 8 × 32kHz = 0.288 W (per MOSFET). If we assume RDS(ON) of 20mΩ and a duty cycle of 50%, then the I2R losses will be 3A2 × 0.02Ω × 0.5 = 90 mW (again, per MOSFET). Together, the two active FETs at any given moment are going to be dissipating about 2/3 watt of power because of the switching.
Ultimately, it's a tradeoff between how efficient you want the circuit to be and how much effort you want to put into optimizing it.
TI offers some isolation gate drivers that let your do exactly this, without destroying yourself or the other circuits.
Also, beware of the minimum clearances for this type of circuit.
Best Answer
Here's a crafted design (except that I kind of ... roughed out ... the speed-up paths.) I am not worried about base oscillation of cascode \$Q_3\$ here, so I didn't do anything for it. It should be fine. If it turns out to be a problem, insert a \$68\:\Omega\$ to \$220\:\Omega\$ resistor between the base of \$Q_3\$ and the \$3.3\:\text{V}\$ supply rail.
simulate this circuit – Schematic created using CircuitLab
Worst case dissipation of any of the BJTs is probably under \$50\:\text{mW}\$, so they should be fine in open air as TO-92s. Perhaps a \$10^\circ\text{C}\$ rise?
Not shown, but probably needed will be some bypass capacitance -- I'd start with \$100\:\mu\text{F}\$ -- across the emitters of \$Q_1\$ and \$Q_2\$. Use short wiring, keep it tight, and probably use dead-bug style wiring.
Rise and fall times, of the circuit itself, can be kept near \$200\:\text{ns}\$, I believe. I would not expect worse than \$350\:\text{ns}\$, even with junk box parts. However, your MCU will have something to say about it as it's own I/O will slew at a rate of its own, too. But the edges are usually reasonably fast. I suspect this circuit will match up nicely.