Electronic – high side mosfet offset voltage in Phase shifted full bridge converter

There are many ways to do this using samples and DAC's etc. In terms of an analog approach this can accomplished using what is known as a "all-pass" filter. This is a filter that has uniform amplitude response with frequency but variable phase response with frequency.

The phase angle \$\theta \$ is:

\$ \theta = 180^{\circ} - 2 * arctan(\omega R C)\$

If you operate the circuit at fixed frequency but vary the RC time constant then you might be able to get the effect you want.

The primary issue you have here is that you want voltage control over the angle.

The natural thing to do here would be to put a JFET in here and control the gate with a DC voltage. Usually this would give you a limited variability in the value of R and might not be that useful. However, in this case, since you have that arctan term which is highly non-limear and the fact that you only want up to \$90^{\circ}\$ of phase shift this might be doable.

^{simulate this circuit – Schematic created using CircuitLab}

The R1 in the circuit is to bias the operating point of the RC time constant to be in the control range you'd like. (it does start out at \$180 ^{\circ}\$ after all).

You'd feed in a fixed frequency signal (sinusoid) and get a phase delayed version out.

Another alternative (if you have limited phase shift because of poor JFET control) is to cascade multiple version of this circuit each with the same control voltage. If you get only \$ 30^{\circ}\$ per stage but have 6 stages you could get \$180^{\circ}\$

There's a lot amiss here. The TC4427 is only rated to 18V on the Vdd pin. You don't show what the Vd supply is set at, but it needs to be at the Vcc that is applied to the top FETs so that it can pull the gate up on the P channel FET to turn it off. Vcc with a 12s battery is going to be 40-45V... If Vdd is connected to Vcc, you'd then (assuming that the TC4427 hadn't failed) be applying the full 40+V to the gates - these are only good for 20V. You'd need to generate a high side gate drive supply at Vcc less a suitable drive voltage (10-15V). Lastly, and certainly not least, look at the body diodes on the output FETs - the high side one will always be conducting. The source and drain pins should be swapped.

I'd suggest looking up a reference design for a bridge and gate driver circuit. You can find ones that use drivers that don't need the inverters, have shoot-through protection (that prevent both FETs being on at the same time) and incorporate a bootstrap supply for the high side FET). Most use N channel only, since the Rds of the N channel FETs is a lot lower.