Electronic – High side switching bizarre side effects

K.,

All the answers for your questions depends about somethings, like this:

• What Transistor would you use?
• You want to control the load current (limit the load current) or you want that transistors operates like a fully on switch?

To dimensionate the resistors, you will need to read the transistors datasheet, and search for the hfe or β, the amplification of the transistors. So you will use:

Ic = β.Ib, find the Ib and then find the base resistance by Ohm's Law. Remember that you need an Ib greater to the Ib calculated to operate at the fully on mode.

Finnaly, you will find a graphic like this on the transitor datasheet:

So you can obtain the Vce voltage (transistor voltage drop), after you dimensionate your base resistance (you will know Ib);

If you get your load equation in function of the variables I (Ic) and Vce, you can construct another curve into the above image, like below:

Example: If your load is a Rl resistance, you will get the equation:

I = (5 - Vce)/Rl

So you will determinate whit precision your Quiescent point, that is the point of operation of your circuit!

Just a tip: Do you know any Spice simulators? Whit them you can simulate your circuits, whit a model for each component, and discovers how your system will work at many situations, it's a very useful tool! I use the simetrix simulator!

EDIT: Looks like it's not a leaky fet, and the voltage difference was just an intentionally introduced offset on the scope. I have built this circuit but with a dummy load and it does not show the mysterious oscillation seen on the plot. I have no idea what is causing it, but my guess is some interaction with the load or power source, or maybe if there were serious parasitics somewhere in the layout, though that seems less likely. Sorry!

The circuit is fine. In fact, it works great, I built it myself just to make sure before writing this.

M1 is a leaky mosfet. It's bad. Those tiny small signal FETs are notoriously sensitive to ESD damage, especially gate to source or drain damage. The oxide layers are extremely thin and it takes very little 'oomph' behind an ESD to punch a hole through it. It's a 100V FET, ESD is 'lots more' of volts. Even bigger, beefier FETs are relatively fragile for gate to source or drain damage.

We can deduce this from several small clues:

1. The drain voltage should not be following VCCP. It should be VCCP, nearly so. That MOSFET has a leakage current of 1µA from drain to source when turned off, which with the resistors taken into account, should cause the drain to track VCCP within 2mV. Yet your plot shows ~2.3V-2.5V difference. That means there is 3 orders of magnitude more current flowing than the typical leakage of M1.

2. VCCP_FSFA is seeing significant voltage, meaning Q1 is slightly turned on, operating in its linear region, and so we see VCCP_FSFA also following VCCP, albeit with a huge voltage drop, before (I assume) pfcOK goes high.

3. There is always voltage on VCCP_FSFA, even when the system is supposed to be completely 'off'. Look - the ground level of the yellow line at the end and the flat part of VCCP_FSFA at the start are not even. It looks like there is a whole volt or thereabouts on VCCP_FSFA, which would not happen without significant leakage.

4. The voltage difference between M1's drain and VCCP tracks roughly what it would if, say, a whole was punched through the oxide layer between the gate and the drain. If we assume there is a path through the 10K resistor to ground from the drain (which there potentially would be in a leaky fet, depending on where the leak was), you get a very similar drop. I had to fudge this by putting a 10K resistor from drain to ground, as a leaky MOSFET generally still works mostly, but with a leaky path simulated by the extra resistor. Simply shorting the drain to the gate in a non-leaky FET will, of course, not give these results at all.

Anyway, you can confirm this fairly easily. Replace the MOSFET M1 with a suitable replacement that you know works, and it should work fine. Regardless, we do not need to test it - the plot of your oscilloscope confirms there is significant leakage in your mosfet. Rough/oscillating turn-ons are a hallmark symptom of a leaky FET.