An electrolytic capacitor doesn't like higher voltage at its opposite terminal i.e higher voltage should only be at positive terminal as per convention.If that so how the capacitor survives in this circuit as AC signal travels in either direction.The capacitor should die in negative cycle.Why it is not happening?
simulate this circuit – Schematic created using CircuitLab
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Best Answer
If you do a small signal analysis the capacitor sees a small negative voltage, however that is actually on top of the bias which is a relatively large positive voltage (5V or something like that). The voltage across C2 can never be negative for a passive load.
Presumably you would add a collector load resistor in order to see some output, because there will be none at the collector and precious little at the emitter.
Note: That's assuming "normal" conditions. If you feed a 10kV 1kHz sine wave into the circuit you will see negative voltage across the 100uF cap, but other bad things will likely be happening too