Electronic – How are differential inputs setup in a differential amplifier


I was struggling to understand what common mode voltage and CMRR is. I think eventually I understand what it is about. Before posing my new question I will briefly write about my drawing. On the left side in setup 1 varying v1 and v2 with respect to ground are applied as inputs of a differential amplifier. And at time "t" v1=5V and v2=1V. It means the amplifier will reject (5+1) / 2 = 3V common-mode voltage (at time t) and take the signals as +2V and -2V inputs (vd = 4V difference).

Differential amplifier schematic

In setup 2 (kind of equivalent to setup 1) at time "t" v1'= +2V and v2'=-2V are applied as inputs of a differential amplifier. Similarly in this case vd = 4V potential difference between the inputs. But because in this case the common-mode voltage vcm=0 it looks like this measurement is more accurate because even it is non-ideal amplifier (having a common mode gain) it will not affect output voltage because vcm=0.

If I have a sensor like a strain gauge which setup is realistic in real life? In data acquisition systems when they use differential inputs instead of single inputs does that correspond to setup 2? Will v1 and v2 always at any time t be as such v1=-v2? I'm a bit confused relating to the real scenario.

Best Answer

You seem to be suffering from a common misunderstanding about what actually makes differential inputs useful. When we have differential inputs, what we really care about is that the impedances of each half of the differential pair are balanced.

Too many descriptions of this sort of circuit illustrate a differential input with two signals, with equal magnitude but opposite polarity, which isn't wrong, but it fails to draw attention to how these circuits actually work. Example:

plot of differential signal

Notice that the input signal is fed into two buffers, one of them inverting. You can do this, and indeed this is a balanced signal, but it's not because the voltage on the "-" input is inverted: it's because (ostensibly) the two buffers used here have equal output impedances, and the input impedances on the differential amplifier are equal. Here are some more examples:


simulate this circuit – Schematic created using CircuitLab

Although both A and B have voltages at the differential amplifier's input that are equal in magnitude but opposite in phase, B is not balanced. This is because the line impedances (set by R3 and R4) are not equal. When this differential line is subjected to noise from an external source, unequal voltages will be induced on each half of the differential pair, and thus noise will not be common mode, and will not be rejected by the differential amplifier.

On the other hand, D depicts a typical case of a single-ended, ground-referenced signal. D is not balanced either, because again the impedances are not equal. However, C presents the same voltages to the differential input, yet C is balanced, because the impedances are equal. Although the signal (represented by V3) is not "centered" on ground, and the resulting voltages at U8 contain the signal in differential mode, plus half the signal in common mode, this is still balanced. The signal is still amplified, and noise is still rejected, which is just what you want.

As far as what you will encounter in practice, the answer is you may encounter either. Each of A and C can be made to work well, depending on the application's requirements. (What range of frequencies? How much dynamic range is necessary?) If you understand why differential amplifiers are useful, and what a balanced signal really is, you will realize that the common mode voltage at the receiver inputs doesn't matter.

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