My question is about CPLDs in general, but take for example this cheap Xilinx one.
I understand that unlike a microcontroller, a CPLD does not have a clock; external edges activate the logic immediately, without waiting around for an interrupt dispatcher to create a context switch and call a function.
On the unit linked above, the "max" Tpd is shown as being 10ns. Does that mean it's literally anywhere from 0ns to 10ns on a given edge, or is it more consistent within a certain set of environmental conditions? Which conditions would affect that delay most heavily?
Best Answer
The delay specification in a CPLD is the maximum (i.e. worst case) pin-to-pin delay. That is, the maximum delay it takes for a signal "edge" to propagate from any pin to any other pin through the internal (combinational) logic.
Saying that a CPLD doesn't have a clock is misguided; you can use a pin as a clock input to feed sequential logic. Comparing it to a microcontroller is also not really suitable, since CPLDs implement hardware, not software.