My question is about CPLDs in general, but take for example this cheap Xilinx one.
I understand that unlike a microcontroller, a CPLD does not have a clock; external edges activate the logic immediately, without waiting around for an interrupt dispatcher to create a context switch and call a function.
On the unit linked above, the "max" Tpd is shown as being 10ns. Does that mean it's literally anywhere from 0ns to 10ns on a given edge, or is it more consistent within a certain set of environmental conditions? Which conditions would affect that delay most heavily?