Electronic – How does modules in an asynchronous circuit know when to signal that their output is ready

digital-logicmicrocontrollerpropagationtransistors

I have recently become fascinated by asynchronous CPUs, which have no central clock and each module instead sends a signal, when their data has been processed. However, I have been wondering how such modules actually know when their output is ready and stable?

In the following example of an asynchronous sequential circuit, some modules communicate using a simple handshake protocol as follows:

  1. A module is triggered by a READY signal from a previous module.
  2. The module then starts manipulating the input data.
  3. The RECEIVED signal is sent to the previous module, when the input has been read and can be modified by the prevous module.
  4. When the output is updated and stable, a READY signal is sent to the next module.
  5. When the RECEIVED signal is sent as a reply, the process starts over.

schematic

simulate this circuit – Schematic created using CircuitLab

  • Is it possible to send a READY signal when the output of a module is stable, without specifically timing the propagation delay of the module circuit?
    • If not, what would be the simplest way of delaying a READY signal based on a circuit's worst case propagation delay?

Best Answer

Is it possible to send a READY signal when the output of a module is stable, without specifically timing the propagation delay of the module circuit?

No.

If not, what would be the simplest way of delaying a READY signal based on a circuit's worst case propagation delay?

For each module, you have a matched delay line made up of a series of AND gates setup as buffers.

See images below:

enter image description here

enter image description here

enter image description here

Related Topic