1) The article says T5 serves as a surge protector. But if the gate is connected to the bottom of RS (RS-SEL in this schematic), wouldn't the
Vgs of the JFET be 1V? Therefore, the FET would never turn on under
normal conditions, which kind of defeats the current source? I'm
obviously missing something.
They're pulling a bit of a trick here — a JFET can also function as an ordinary diode. For example, look at T9 down below. If a positive surge is applied to K2, the gate-channel junction of T5 will be forward biased, which connects it directly to the output of the opamp, a low-impedance point.
The advantage of doing this is that in normal operation, T6 has very little leakage and very little capacitance, so that it doesn't disrupt the low-current settings.
Remember that a JFET is a depletion-mode device. It will conduct current unless the gate is driven more negative than the channel (relative to either the source or drain terminal) by the specified threshold voltage. With a VGS of -1V, the FET still conducts. The drain-source resistance doesn't upset normal operation because of negative feedback, IC6 will raise its output voltage to the level required to force the desired current through RS.
2) According to the article, all of the source current from IC6 travels through R59 as long as the user-selected current is 100uA or
less. I believe I understand that because at 100uA, Vbe of T6 would be
360mV, which is less than Vbe(on) for T6, so T6 would be off. But
wouldn't R59 contribute a very large error in series with R28? The
combined resistance of R59 and R28 is 13.6k, which would result in a
current of 1V/(10k+3.6k) = 73.5uA. That's pretty far from 100uA.
No, because R59 is inside the feedback loop for IC6, the opamp automatically compensates for its effects.
3) For user-selected currents above 100uA, how does R59 and T6 affect the voltage going into the resistors downstream? Wouldn't they
contribute significant voltage drops that mess up the 1V reference
calculations? I can't figure out an intuitive feeling for how the
resistor and transistor work together here.
Again, because of negative feedback, when T6 conducts, IC6 reduces its output voltage to maintain the correct voltage across RS.
The general principle is that components between the output of the opamp and the feedback point don't matter (within certain limits), because the opamp will act to reverse their effects and maintain the desired voltage at the feedback point. It can be tricky sometimes to understand exactly where the "feedback point" is in some circuits. In this case, it is the node labeled TP6.
This appears to be a standard MOSFET low-side switch circuit. An N-channel MOSFET conducts from drain to source when the gate voltage is higher than the source voltage by a certain amount. When the voltages are equal, current cannot flow from drain to source (it is an open circuit).
The 15k resistor weakly pulls the gate voltage down to source voltage, thus insuring that the transistor will be off, UNLESS the momentary switch, S1, is on. S1 is a pushbutton type of switch. When you press it, it is on, and when you let go, it turns off by spring action. In this circuit, pressing S1 will cause the MOSFET to turn on because it will elevate the gate voltage above the source voltage.
When the MOSFET is off, there is no conductive path for the current through whatever that thing is that says ATTY. When you push the button (S1) the gate of the MOSFET will be driven high compared to the source, and the MOSFET will conduct current from drain to source, thus completing the circuit and energizing ATTY.
The basic idea of the circuit is sound. Just need to make sure the MOSFET can handle the relevant voltages and currents.
Best Answer
The schematic is incorrect, and you are absolutely correct the output current can never be zero with the schematic as shown.
Consider two cases:
The BSC... is off completely (this might be when Vshunt is 0 V but we can ignore this for the moment). Under these condition the 50 uA reference current flows through the 10k to the output pin (and we have to assume here the output is shorted to ground to make things easy). The voltage developed into the error amplifier is 0.5 V .....so the (PWM generated) current through the 0.1 Ohm resistor is 5 A (there will be ripple associated with this, but lets ignore for the moment). ....so far so good, we can get to 5 A.
The BSC... is saturated, and since there is (essentially) no current from the gate side of the device, the 10k Ohm resistors are effectively in parallel and the reference voltage developed is 0.25 V. ...so the (PWM generated) current through the 0.1 Ohm resistor is 2.5 A.
So the schematic as shown does not match the graph they produced.
Now under what condition could the reference voltage into the error amplifier produce zero current through the 0.1 Ohm resistor?
If the reference voltage was zero, then the PWM would never switch on, so the current would fall to zero (once the 47 uf capacitor discharges).
To achieve a 0 V reference voltage into the error amplifier you need to divert all the 50 uA reference current to ground.
Could the LTC2054 and BSC... shunt the current? Not as shown, but if the current source was powered from a negative supply it could. If Vshunt is 0.5 v, then the BSC... is a constant current generator of 50 uA ...so we have the right current, but the ground shown for the constant current generator would have to be at least -0.5 V to be able to pull the voltage reference at the error amp down to zero.
I'd suggest the current generator could include a negative power supply of at least 1 V to be viable. This makes it less easy to generate the Vshunt, but still quite possible.
So something like this would work:
Now last thing consider the impact of a load resistance (remember I considered the load as a short circuit in all the above).
As load (resistance or offset) goes up, there will be a voltage developed at the output, and this will raise one end of the 10 K resistor. Using the alterations I proposed above, it does not matter what the output voltage is, since we only offset the voltage created between the output end of the 0.1 Ohm sense resistor and the reference voltage into the error amp.
For example, consider you were using this current generator to characterize the forward voltage of a power diode. The voltage on the output would rise to quite high (0.7 to 1 V or more) depending on the current through the device. Providing the input voltage supply is high enough then there would be no problems with higher output voltages with the LTC2054 as a pure current source. You can also get to zero current (within practical limitations) using the Vshunt voltage 0 to 0.5 V.
PS: as a significant side note to make your head spin, the schematic as shown would work at very small output currents (but unlikely to go to zero) if the output voltage were higher than 0.5 V. So in the case of a diode or zener being tested where the output voltage is over 0.5 V the Vshunt generator would work as shown in the application note. It just won't work into a resistive load where the output voltage drops below 0.5 V.
Implementing a fix
The LT2054 is a very high quality op-amp, with very low offsets.
One possible fix to get you close to zero current would be to drop the 10k Ohm resistor to 100 Ohms. Now the voltage drop to sink the 50 uA is just 5 mV.
If you want to keep the 0 - 0.5 V as the Vshunt then a 100:1 resistive divider could work.
Something like this:
simulate this circuit – Schematic created using CircuitLab