Electronic – How is byte addressable memory implemented

Yes, your solutions for the homework are correct. Note that for the 4Mx32 you only use 8 bits per 32 bit word. If you want to use all bits you'd need a 32-to-8 multiplexer/demultiplexer.

#2 and #3 of the lecture are a bit confusing. If the memory is word-addressable with 16-bit words, it's no longer a 4Mx8 memory but a 2Mx16 memory. To address 2M words you need 21 bits. Similar for #3.

While the problem does not specifically say so, you can typically assume word-addressable memory when dealing with this kind of cache problem. Thus, in order to calculate the size of the offset, you need to know the size of a block in words, which in this case is given as 2. Thus, you need 1 bit (clog2[block_size_in_words]) to determine which of the 2 words in a block you are addressing, as the problem solution uses.

Your analysis for the number of sets seems accurate, but just to be clear: as we know the total size of the cache is 12 blocks (24 words / 2 words per block) and there are 3 blocks per set, there must be 4 sets (12 blocks / 3 blocks per set). Thus, you need 2 bits (clog2[number_of_sets]) to index the sets.

Its important to note that the size of a word is architecture-dependent. A word can be any number of bits long, typically 8, 16, 24, 32 or 64 depending on the processor (See: http://en.wikipedia.org/wiki/Word_(computer_architecture)). The problem does not define a word size, so you cannot determine how big the blocks are in bytes. As you said, they could be 8 bytes with a 32-bit word, but they could be 4 bytes with a 16-bit word. As the problem did not specify the word-size, you cannot assume you know it unless it is specified somewhere else that applies to the problem (ie, the professor says to always assume a 32-bit word size in this class/on this test).