Electronic – How is this EEPROM fully addressable

Please check page 15 through 18 of the datasheet. You'll find some Diagrams which explain the procedures involved quite good. Also there are timing diagrams on page 12 and 13.

For example, to erase the chip you have to do the following:

1. Set A9 and OE#/VPP to 12V
2. Hold CE# low for at least 100ms
3. Remove 12V from A9 and OE#/VPP
4. Wait a moment (1µs)
5. Check all addresses for 0xFF (If this fails, there was some problem with the erase operation)

For programming you do the following:

1. Set OE#/VPP to 12V
2. Set Byte Address on A0-A15
3. Set data on D0-D7
4. Pulse CE# low for 20µs
5. Go back to 2. for more data
6. Remove 12V from OE#/VPP
7. Wait a moment (1µs)
8. Check all written data

These 256K x 1 chips are only 1 bit wide. With four of them you would only get 1 nibble at a time, and the Z80 doesn't do 4-bit data.

It is possible to use them, but not what I'd call practical, and would take far more than 8 chips, unless you want to use an FPGA to make a RAM controller. You need a controller anyways, in order to generate your dynamic RAM timing. But let's concentrate on simple read/write operations.

You need, at a minimum, a 9-channel 2x1 multiplexer for the addresses. You also need some time delays to generate RAS and CAS strobes. With a single 41256 you could produce a 32K x 8 RAM, by using page mode. Using the upper 15 address bits as the 32K address and the 3 lsbs of address to provide the 8 bits of data, you would perform a page mode read or write , then step through the 3 data addresses to sequentially read or write the 8 data bits into or from the RAM. Page mode cycle time takes 100 to 150 nsec/cycle, depending on your chip speed, so a single read or write cycle would take on the order of 1 to 1.5 usec.

Chip count would be something like: 2 ea. 74HC157 2-1 mpx (although this would restrict you to a 16k equivalent), 1 ea 74HC374 for the RAS addresses, 2 ea 74HC161 for the CAS addresses, 1 ea. 74HC161 for the data bit counter, 1 ea 74HC151 8-1 mpx for writing data, 1 ea 74HC374 as a read shift register to store the output data before sending it to the Z80, and a 74HC244/245 to drive the data onto the Z80 data bus. Plus a few more for glue logic, at a guess. That's a minimum of about 11 chips. Plus, assuming you're using an 8-MHz Z80, it will run at an equivalent of about a 2-MHz chip. All your memory reads and writes will take a loooong time.

You can, of course, speed things up by using 4 of them with a two-stage read or write cycle with almost no loss in speed.

What you really need to do is use 8. Then you have a good match between your CPU and your memory, and you should be able to get decent speed and minimal chip count.