Is there a maximum number of i2c slaves that a i2c master can drive? What are the physical limiting factors?
Electronic – How many i2c slaves can a i2c master support
i2c
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As I understand it you want to send different data to each of the slaves, but the slaves don't have to send data back.
I2C is an addressed bus, so if you assign a different I2C address to each of the slaves you'll need only two wires to send the data. If needed you can ask data back as well. The Arduino's AVRs have an I2C compatible serial bus. And you can extend to more than 3 slaves without extra hardware, up to a maximum of 127.
UARTs don't have addressing, so you would need either 3 UARTs (which the AVR doesn't have), or add external logic to switch between UART lines (which costs money). Each additional slave means extra cost. Not recommended.
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Like Chris says you can use UART to create a multidrop bus. And then you'll have to add addressing, which makes your UART work a bit like I2C, but then asynchronous, and without address matching hardware like the I2C has. So still not really an advantage.
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SPI also uses shared lines for data: a single MOSI, and the MISO lines connected. To address each slave individually you'll need one SS (Slave Select) line per slave. So that's at least 5 I/Os: MOSI, SCK, 3 \$\times\$ SS, and MISO if you also want to read data from the slaves. Each additional slave adds 1 I/O pin on the master.
I think the I2C is the best solution, requiring the least number of wires. The protocol is a bit more complex than UART or SPI, but since the AVR has the hardware for it, it should be easy to use.
It's fine so long as you only run the bus as fast as the slowest device on the bus. So in your case, it would work so long as you always run the bus at 50 kbit/sec, even when addressing a part that is capable of running faster. If you try to run a bus at, say, 400 kbit/sec with a device only rated to 50 kbit/sec on it, it is possible that the device may misinterpret some part of the data as a start bit and then cause trouble with the transmission. Basically, you have three choices: run the bus slow, segment the bus with multiple I2C controllers or an I2C mux, or swap out the slow devices for faster ones.
Note that this is less of a problem with SPI devices as SPI uses an explicit chip select line for each device. In this case, it is possible for an SPI bus to run faster than the slowest device, so long as the selected device can handle the speed.
Best Answer
The software limiting factor is the size of the address used for the slaves: 7-bit or 10-bit, which support 127 and 1023 devices, respectively. Physically, there are two restrictions. First, the physical size of the bus because the bus is only meant for short runs (the inter IC part). If the bus is too large there are capacitive loading and propagation delay effects that need to be dealt with. Second, some devices can't support the full range of I2C addresses. As examples, the MPU6050 gyroscope only supports two addresses, and some devices reserve specific addresses for special purposes.