Electronic – How much current can a 74HC00 supply

digital-logic

I'm trying to figure out what kind of current a single logic gate can supply. I'm looking at this datasheet:

http://www.ti.com/lit/ds/symlink/sn74hc00.pdf

I see in section 6.1 it says "IO = ±25 mA", but that's the section on "absolute maximums". In particular, the device isn't guaranteed to work at that level, it's just guaranteed to not immediately break. (It's not even guaranteed that it won't break; just that it won't break straight away.)

Section 6.3, "recommended conditions", doesn't seem to say anything about current at all. (I'm assuming that current is denoted by symbols containing "I".)

Section 6.5 has "II" (input current?) in nano-amps (…so, the inputs draw really small current?). It also lists "ICC" (total chip package current?) which is only in nano-amps. Presumably the maximum output current must be smaller than this. (?)

In short, I don't see the number I'm looking for anywhere on the datasheet. Am I being blind or something?

I'd particularly like to know what the maximum allowable fan-out is.

Best Answer

The VOL/VOH specifications show how large the worst-case voltage drop can be at the specified current. You can try to draw larger currents, up to the absolute maximum rating, but then there is no longer a guarantee about the voltage drop.

For smaller currents, the output transistors (MOSFETs) behave like a resistor, so you can just interpolate the worst-case voltage drop.

The application note Input and Output Characteristics of Digital Integrated Circuits at 5-V Supply Voltage shows typical (not guaranteed) values for the voltage drop:

74HC output voltage vs. output current

The application note HCMOS Design Considerations says:

High-speed CMOS can support up to 10 LS loads from a single standard output […] From the dc values in the individual data sheets, the fan-out of high-speed CMOS devices is unlimited for all practical purposes. However, from an ac point of view, there is a definite limit to the fan-out. The limiting constraint is the input rise time.
[… Lots of math] indicates that the maximum fan-out of high-speed CMOS devices is approximately 505.