I'm looking at this datasheet, which has this graph on page 3:
The FET has an \$R_{DS(on)}\$ of \$14 m\Omega\$; how can \$V_{DS}\$ be > 10 V at 100 A? Shouldn't that be 1.4 V? And if it was 10 V, wouldn't the FET evaporate at 100 A = 1000 W?
Electronic – How must I read this MOSFET specification
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This difference could be explained in a number of ways, though none definitive without knowing more about the device than the datasheet (necessarily) reveals. These may include differences between the actual structures of the underlying devices within the packaging (most likely), as well as differences in the estimations, testing practices, and / or acceptable margins of the companies or even specific engineers involved in their design and documentation. It is conceivable that typos in the actual datasheets themselves could be blamed. Nothing is certain until it can be proven that it works, and even then, things (manufacturing processes, etc) can change over time without you (or even the distributor, documentarian) necessarily being informed. Good testing procedures, performed on all devices prior to distribution (i.e. quality control) and wide operational margins for parts selection can help to insulate you from problems inherent in both mis-specification and changes in manufacturing over time, but don't be surprised if your (initial) design requires re-work somewhere along the line because of these things.
The SOA for this FET shows an additional limitation (beyond the traditional Vds, Imax, Rds, and P lines), that is not commonly found in other MOSFETs: the lines under the 10 ms and 1 ms markers. The only possible reason for this limitation that I found appears on the last page of IXYS Power MOSFET Datasheet Parameters Definition:
" These theoretical constant power curves are derived from calculation with assumption of essentially uniform junction temperature across the Power MOSFET die. This assumption is not always valid, especially for a large die MOSFETs. ...(more explanation)... Modern Power MOSFETs optimized for a switch-mode applications were found to have limited capability to operate in the right-side bottom corner of the FBSOA graph."
Note that this transistor is intended for switching, not for linear operation, so it is probably optimized for that task: it is not designed for operating for longer time in this lower-right corner of the SOA. Note also that for small times (< 10us, as occur in switching) there is essentially no such lower-right-hand-corner limitation.
For comparison: the SOA of a random MSOFET (irf7146):
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The 14 mOhm you mention is valid when Vgs >= 10V (in other words, the FET is fully turned on). The graph you show illustrates the FETs behaviour for Vgs in the range 2..8V, the range in which the FET is between fully off and fully on. In this operational mode the Isd is determined mostly by the Vgs (the FET behaves as a voltage-controlled constant current source). For this mode to work there must be a minimal Vds, otherwise that voltage would be the limiting factor for the Isd. Hence the Vds >= 10V requirement.