I'm absolutelty no FPGA expert, but designed a device with Quartus and used Modelsim to simulate it. I was then told to modify the design and make it work with a Lattice device as they changed their mind about Altera (mainly down to Lattice devices being a bucket load cheaper I think).
Unfortunatelty (for me) Lattice Diamond comes with this Aldec-HDL program instead of Modelsim. After stuggling for a couple of days I have managed to finally work out how to be able to tweak my workbench and re-run the simulation without having to relaunch [Active HDL] from Diamond. However, after a further couple of days of trying, I just cannot work out how to add internal signals to the waveform viewer.
On Modelsim one of the few intuitive features is that you can select an instantiation of a particular component, pick one or more of its signals and just add it to the waveform viewer. On Active-HDL I can't even find a way of picking a particular instantiation of a module. I can find a way of picking a module, but its signals just say "Unavailable". That doesn't seem particularly helpful anyway as you need to be able to select an instantiation of a component, not just the component definition.
I assume this must be possible, otherwise it's a pretty useless simulator. Can anyone enlighten me on how to do this please?
Best Answer
OK, always seems weird answering your own question, but this might save people a lot of time in the future.
The big important thing here is that in Design | Settings | Access to Design Objects, you must UNTICK "Limit Read Access to design top level signal only".
Then, once you have compiled the the testbench you can add all/any signals from the instantiated units that appear in the Structure Tab when simulation is initialised.
Obv, really.
Hope this stops other people going insane.