Electronic – How to conclude region of operation for a series combination of MOSFET

What do you mean by "input characteristics"?

Textbooks and datasheets describe the behavior of MOSFETs using two graphs:

• Output characteristics: \$I_D\$ versus \$V_{DS}\$ with \$V_{GS}\$ as parameter.

• Transfer characteristic: \$I_{D}\$ versus \$V_{GS}\$ at a given fixed \$V_{DS}\$ value (this latter is chosen so that the MOSFET is in saturation region).

There is no "input characteristic" (such as the \$I_B\$ versus \$V_{BE}\$ curve of a BJT) because the other input quantity besides \$V_{GS}\$, namely \$I_G\$, is virtually zero at DC (and all these curves assume DC operations). Therefore it wouldn't make much sense to plot \$I_G\$ versus \$V_{GS}\$, unless you wanted to analyze leakage gate current, but I assume you are not interested in that.

So it is clear (also by a comment of yours) that by input characteristic you mean the transfer characteristic (TC). Note that the TC is plotted with a fixed drain-source voltage that guarantees that the MOSFET is in saturation for each \$V_{GS}\$ value on the horizontal axis. This is done because the TC is useful when the MOSFET is in saturation, i.e. when the output current depends solely on the input voltage (not considering "Early effect"), for example when you want to use the MOSFET as an amplifier and you need to draw a load line to design its bias circuit.

If you plot the TC for different values of \$V_{DS}\$ you get a family of TC curves. For example consider this circuit simulation with LTspice:

Plotting the TC for different \$V_{DS}\$ values you get:

As you can see, the more you increase \$V_{DS}\$ the more the curve resembles a parabola, as you would expect for the TC in saturation. Notice that this part shows a threshold voltage \$V_{th} \approx 4V\$.

Let's consider what happens if \$V_{DS}\$ is not big enough to drive the MOSFET in saturation for every \$V_{GS}\$ value, like in the lowest blue curve (Note: to present a more revealing plot I selected the curve corresponding to \$V_{DS} = 2V\$, whereas the lowest blue curve above corresponds to \$V_{DS} = 1V\$):

As you can see, in saturation region you get a quadratic curve, whereas in triode region you get a linear curve. Everything as expected, except that real devices don't have an abrupt change between the two regions and that the linearity of the triode region is not perfect because of the device not being ideal (SPICE models usually take into account these effects).

If you see in your simulation an abrupt departure from this behavior it could be that you tried plotting the curves outside the range of the voltages/currents admissible for your device. Notice that I limited the first plot to max 14A/20V which are the absolute maximum ratings for the device I chose. If you don't keep this in mind you will destroy the device (in real life) or get odd results (in simulations).

EDIT (in response to a comment and a question edit)

You ask why the "perfectly" linear curve for \$I_D\$ versus \$V_{GS}\$ in ohmic region is not exploited. Here is some insight:

Why do you need a linear characteristic between input (\$V_{GS}\$) and output (\$I_D\$)? Usually to use the device as a (linear) amplifier. But what are the conditions that allows to have that linearity? \$V_{DS}\$ must be held constant. Therefore to make an amplifier this way you have to insert a load in the output circuit and still keep \$V_{DS}\$ constant. You can understand that such a load cannot be a simple resistor (which is the simplest kind of load). Therefore you need a much more complex circuit (with other active devices).

On the other side, you can use the same MOSFET biased in saturation and get a decent linear amplifier: even if the behavior of the device is not intrinsically linear, but quadratic, there are linearization techniques (e.g. employ simple feedback schemes, like a resistor in series with the source terminal) that allow the overall amplifier to become more linear.

Let me answer your question focusing on a enhancement n-channel MOSFET, or nMOSFET, since every other case can be derived from it.

First off, consider that every MOSFET is a 4 terminal device, although the discrete component you can buy on mouser or RS alway come with 3 pins.

The B terminal is called body or bulk, and it is a p doped region in a nMOSFET, n doped region in a pMOSFET. In commercial discrete transistors it is usually tied to the source, hence the 3 pins for a 4 terminal device.

Back to your question, for a nMOSFET the S and D regions are highly doped n, usually indicated with n+. The gate body voltage, Vgb, controls the channel under the oxide (the white-ish layer under the gate) between the drain and source.

Since in a 3 pin MOSFET the source is connected to the body, Vgb = Vgs and that's why everybody refers to the gate source voltage as the controlling signal.

Now, there are roughly 3 region for the channel under the the oxide:

1. Accumulation: Vgb < 0 the channel has plenty of free holes available for conduction, but in the n-p-n series between source-channel-drain there is always a reversed biased diode, hence there is no conduction.
2. Depletion: Vgb < Vt the channel is emptied of free carriers and it is highly resistive.
3. Inversion: Vgb > Vt the channel has plenty of free electrons, and effectively is a n region.

1 and 2 are the cutoff region, while linear and saturation happen in 3, when the channel is inverted. As a side note, this is the reason why this device is called n channel MOSFET, because when it conducts the channel is inverted from p to n.

You can find a more in depth, but still qualitative, explanation here.