Electronic – How to design a discrete linear regulator with an opamp and an N-channel MOSFET

1. A resistive load is not a bad model for headphones. If you wanted to be pedantic, you could add inductance for the speaker coils and parasitic L, C, R for the cabling, but a simple resistor is okay. I would look up the impedance your headphones and use the manufacturer supplied impedance.

2. I would consider R10 & R11 as a form of current limiting. Here's why. (I'm using the reference designators of the SGA-SOA-2 original schematic on sg-acoustics for this question, assume reference designators according to your schematic for the rest) The branch formed by Q6 & Q7 is the output stage of the op-amp. We know V_be6 + V_R10 = V_d5 + V_d6. V_d is related to the diode current in a logarithmic relation, and thus V_d5 + V_d6 will not change appreciably. Thus we can say V_be6 + V_R10 = constant. Thus at high output currents, R10 will take the voltage drop and decrease V_be6, thus limiting the amount of current that can flow through the output stage. This is good for protecting against short circuits. That's my guess anyways, it is a bit strange for short circuit protection, typically we see another transistor monitoring R10 and then shorting out V_be6. See (http://users.ece.gatech.edu/mleach/lowtim/prot.html, figure 3).

3. R8 implements Emitter Degeneration. There's a lot to be said on this topic, searching for common emitter with emitter degeneration will generate a lot of resources. The high level idea is we use R8 to set the bias current of the transistor because without it, the gain of the common emitter amplifier (Q7) is very sensitive to V_be7 and makes it difficult to break into large signal & small signal models. So R8 stabilizes our amplifier, but it also kills our gain. The voltage gain of the emitter degenerated common emitter amplifier is -R_C / R_E where R_C is the collector resistance and R_E is the emitter resistance. You can see that as R_E increases the gain decreases. This is bad as this amplifier stage provides the majority of the op-amp gain. In order to fix this, we use bypass capacitor C1. Capacitors have impedance 1 / (jwC) so at low frequency, it has very high impedance and at high frequency, there is low impedance. Let's just examine the DC (biasing case). At DC, C1 has high impedance and the parallel network C1 || R8 is approximately R8. So at DC, we still have all the benefits of emitter degeneration (basically helping us bias the transistor). At high frequency, we want to have large gain. In this situation, C1 || R8 is now dominated by C1 which has low impedance and C1 "bypasses" or shorts out R8. Now we are back to our standard common emitter amplifier which has much higher gain than the emitter degenerated version. Basically C1 makes the gain of the amplifier frequency dependent so we get both large gain at high frequency and nice biasing of the transistor.

4. Not really, you should expect comparable performance since you are using actual models and not ideal components. I've built discrete op-amps before and they typically match within 10% of simulation results.

5. Yes, certain transistors probably have better noise figures, but I'd be hesitant to say that the transistors themselves are the source of the harmonics instead of the design of the amplifier. I would carefully look at the biasing of the circuit before trying to use better transistors. Remember that if we break our small signal model assumption, we can't assume linearity over the amplifiers. Make sure each of your stages is linear over the range that you expect. Disconnect the output stage and ensure the diff pair + C-E is linear and remember that the input signal must be really small in order to meet your small signal assumption in open loop. Typical op-amp gain might be > 10^4. That means even a 1 mV signal would be amplified to 10 V swing. Test the diff pair & C-E open loop, verify linearity. Crossover distortion should be almost definitely eliminated by the op-amp feedback. If it isn't, then the op-amp gain isn't large enough.

6. Open loop measurements of op-amps are difficult because of the large gain. I would even try going lower to 100 uV. We can only expect linearity if our small signal models are valid, meaning the perturbations around the bias point is small enough that we can linearize. Reiterating what I said for question 5, check the linearity of each stage independently, the diff pair, C-E and output stage. The may mean creating bias circuitry to test each stage separately. If you are running into power rail saturation (running against 18, -18 V), probably check the biasing of the amplifiers to ensure there is enough voltage headroom at the output to allow for swing. If you see distortion, make sure small signal is still valid. Lastly, check the datasheets and make sure you're not running up against any current constraints. These could be in the BJT or part of our design as seen by the current limiting for R10, R11.

There's actually (perhaps) nothing wrong with using a PNP BJT in this application. You just use a resistor that corresponds to the maximum collector current (minimum resistance). In your circuit above, 7.5K would be fine. Typically the voltage drop would be in the 50mV range or less. If ~0.05V drop isn't a problem then the BJT is fine.

It's okay to use a lower base resistance than required by the collector current, just not larger (subject to other limitations, which don't apply here).