Electronic – How to fix the glitches in the following Karnaugh maps

digital-logicglitchkarnaugh map

The following circuit is supposed to output 1 if the input is greater or equal than 1010 (decimal 10). The truth table is given and we are supposed to convert that to POS and SOP using Karnaugh maps. Here's the truth table with the minterms and the Maxterms:

Here's the Karnaugh map I did for the SOP (Sum of Products)

Same for POS (Product of Sums)

I remember my professor saying that when you make groups on the Karnaugh map if there's adjacent groups there will be a glitch.

I have three questions:

Is it possible to fix the glitch without the Karnaugh map? If yes how?
How do you fix the glitches on the Karnaugh map?
How do you fix the glitches on the resulting circuits (I have to make one for the POS and one for the SOP).

Best Answer

The term for this glitch effect is hazard. The Karnaugh map is an easy way to identify and eliminate hazards. A hazard exists when there are adjacent, non-overlapping groups (also called terms) in the K-map. When transitioning from one group to the other, the output shouldn't change according to the logic, but there might be a change or glitch because of uneven delays through the gates. If this is not tolerable, eliminate the hazard by defining an additional, redundant term that overlaps the groups, in effect bridging the gap between them.

For example, in your sum-of-products map, you have two terms, ab and ac. These two overlap; there is no hazard.

An example of a hazard: Consider the latch Q = DE + Q 'E (where 'E = not E). The latch function: when E is high, Q = D. When E goes low, Q maintains its level regardless of subsequent level of D. But there is a hazard: when D and E are high, Q is high and should remain high when E goes low. But both product terms change state, and if the DE term goes low before the Q'E term goes high, Q becomes 0. (The K-map will show that the terms do not overlap.)
To eliminate the hazard, add the additional, overlapping term DQ to the sum: Q = DE + Q'E + DQ

Related Solutions

Electronic – How to simplify the actual function using K-maps

Just simply make a truth table that shows values of F for each of the combinations of A, B and C. Then transfer this information to the K-Map format table to do the minimization. enter image description here

Electrical – How to convert multiple Karnaugh maps into a logic gate circuit

Do I combine all of the expressions (as in W+X+Y+Z or WXYZ)

No. What the equations show you are how to derive outputs for four separate pins. If you wanted to combine the four pins you should have done it earlier when coming up with the Karnaugh map (the Karnaugh map would then only have one output instead of four).

First step, treat the four as four separate circuits:

A ─┬───────────────┐
   │               │
B ──┬─[NOT]────────[AND]┐
   ││              │    │
C ────[NOT]──┬─────┘    [OR]── W
   ││        └[OR]─┐    │
D ────────────┘    │    │
   │└──────────────[AND]┘
   └──[NOT]────────┘

 .... implementation of other circuits left as homework

A ──[NOT]────────┐
                 │
B ──[NOT]──┐     [OR]─┐
           [AND]─┘    │
C ──[NOT]──┘          [AND]── Z
                      │
D ────────────────────┘

Second step, join A to A, B to B etc.. This is obvious because obviously A is the same as A etc.

A ─┬────┬───────────────┐
   │    │               │
B ──┬────┬─[NOT]────────[AND]┐
   ││   ││              │    │
C ───┬─────[NOT]──┬─────┘    [OR]── W
   │││  ││        └[OR]─┐    │
D ────┬────────────┘    │    │
   ││││ │└──────────────[AND]┘
   ││││ └──[NOT]────────┘
   ││││
   └───────[NOT]────────┐
    │││                 │
    └──────[NOT]──┐     [OR]─┐
     ││           [AND]─┘    │
     └─────[NOT]──┘          [AND]─ Z
      │                      │
      └──────────────────────┘

 .... implementation of other circuits left as homework

The circuit should be working at this point but if you're paying attention you may notice that some parts of the W and Z circuits are sharing the same logic. For example, we're using NOT on B and C twice. The next (optional) step is to refactor the circuit and remove redundant/repeated subcircuits and components:

A ───┬──────────────────┐
     │                  │
B ────┬─[NOT]──┬────────[AND]┐
     ││        │        │    │
C ──────[NOT]───┬──┬────┘    [OR]── W
     ││        ││  │         │
     ││        ││  [OR]─┐    │
D ─┬───────────────┘    │    │
   │ ││        ││       │    │
   │ │└─────────────────[AND]┘
   │ │         ││       │
   │ └──[NOT]─┬─────────┘
   │          │││
   │          └─────────┐
   │           │└─┐     [OR]─┐
   │           │  [AND]─┘    │
   │           └──┘          [AND]─ Z
   └─────────────────────────┘

 .... implementation of other circuits left as homework

Best Answer

Related Solutions

Electronic – How to simplify the actual function using K-maps

Electrical – How to convert multiple Karnaugh maps into a logic gate circuit

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