The basic reason for using a parallel tuned circuit as the exciter is one of efficiency. If your inductor and tuned capacitor are 33uH and 75nF, resonant frequency will be about 101kHz. If you do the math you'll see that a lossless tuned circuit like this exhibits infinite impedance but still circulates high current between cap and inductor.
Lossless circuit are of course impossible but making the losses as low as possible means that if your inductance is 33uH and your applied voltage is (say) 40VRMS at 100kHz, the current in the inductor is: -
\$\dfrac{40V}{2\cdot\pi\cdot F\cdot L}\$ = 1.93 Amps
Your H bridge won't even be breaking into a sweat because it won't be supplying anything like this current. This current is due to the voltage across the inductor but the capacitor has the effect of performing "power-factor" correction and because the losses are low maybe the H bridge will be supplying in the order of 50mA to a couple of hundred mA.
However, your H bridge is exciting the coil/cap with a square wave and there will be losses due to the harmonics within the square wave. Because of this it makes sense to feed the coil/cap via an inductor too - somewhat smaller than the coil (maybe 1 quarter). You will also need to retune the capacitance to compensate for this. Some experimentation in this is required to get best results but, you should aim to reduce the H bridge's current to avoid it overheating.
I'd also say make one larger coil suitable for all three inductive loads. The larger coil can be any regular shape that suits your requirements for placement of the receiving coils.
Optimum performance is when the receiving coils are also tuned with a capacitor but, because the induced voltage is in series with a receive coil, the tuned circuit behaves like a series tuned circuit and, if the coupling is too great it will heavily detune the transmit coil when it is close by. You should aim for a minimum gap or incorporate circuits in the H bridge that current limit.
I strongly advise you to use something like LTSpice for simulating this - you'll learn a lot about the various interactions. I'd also recommend you read a bit about tesla coils because that is what are are intending to build (when tuned as per my thoughts).
Some things I'd try:
- Use the slowest drive you can get away with. At these clock rates, you should be able to use very slow drivers. You don't mention a specific FPGA type, but if it were Xilinx, I'd be using the "quiet" drivers, or "slow" if not available, and a 4mA drive current. See how it looks on the scope, increase the drive current if necessary.
- Twist a ground wire with each of your signals, or at least with the clock signals. Or if using ribbon cable, put a ground on either side of both the clocks. Keep the clocks well away from each other. In the extreme, use coax for the clocks (but be careful to use a very short connection to ground for the shield, otherwise you stand a good chance of not gaining anything)
You have to think about how the current is flowing - both "out" and "back" - any time the current of one signal mixes with another (say using a single ground return wire), you will have potential for problems.
Another suggestion - in order to understand what's going on so you can predict these problems next time, read (and inwardly digest :) a book on signal integrity
Best Answer
What you can do to increase crosstalk: